TIMERS. TLC556Y Datasheet

TLC556Y Datasheet PDF


Part

TLC556Y

Description

DUAL TIMERS

Manufacture

etcTI

Page 24 Pages
Datasheet
Download TLC556Y Datasheet


TLC556Y Datasheet
TLC556, TLC556Y
DUAL LinCMOSTIMERS
D Very Low Power Consumption . . . 2 mW
Typ at VDD = 5 V
D Capable of Operation in Astable Mode
D CMOS Output Capable of Swinging Rail to
Rail
D High Output-Current Capability
Sink 100 mA Typ
Source 10 mA Typ
D Output Fully Compatible With CMOS, TTL,
and MOS
D Low Supply Current Reduces Spikes
During Output Transitions
D Single-Supply Operation From 2 V to 15 V
D Functionally interchangeable With the
NE556; Has Same Pinout
SLFS047B – FEBRUARY 1984 – REVISED SEPTEMBER 1997
D, J, OR N PACKAGE
(TOP VIEW)
1 DISCH
1 THRES
1 CONT
1 RESET
1 OUT
1 TRIG
GND
1
2
3
4
5
6
7
14 VDD
13 2 DISCH
12 2 THRES
11 2 CONT
10 2 RESET
9 2 OUT
8 2 TRIG
FK PACKAGE
(TOP VIEW)
description
The TLC556 series are monolithic timing circuits
fabricated using the TI LinCMOSprocess, which
provides full compatibility with CMOS, TTL, and
MOS logic and operates at frequencies up to
2 MHz. Accurate time delays and oscillations are
possible with smaller, less-expensive timing
capacitors than the NE556 because of the high
input impedance. Power consumption is low
across the full range of power supply voltages.
1 CONT
NC
1 RESET
NC
1 OUT
3 2 1 20 19
4 18
5 17
6 16
7 15
8 14
9 10 11 12 13
2 THRES
NC
2 CONT
NC
2 RESET
Like the NE556, the TLC556 has a trigger level
NC–No internal connection
approximately one-third of the supply voltage and
a threshold level approximately two-thirds of the supply voltage. These levels can be altered by use of the control
voltage terminal. When the trigger input falls below the trigger level, the flip-flop is set and the output goes high.
If the trigger input is above the trigger level and the threshold input is above the threshold level, the flip-flop is
reset and the output is low. The reset input can override all other inputs and can be used to initiate a new timing
cycle. If the reset input is low, the flip-flop is reset and the output is low. Whenever the output is low, a
low-impedance path is provided between the discharge terminal and ground.
While the CMOS output is capable of sinking over 100 mA and sourcing over 10 mA, the TLC556 exhibits greatly
reduced supply-current spikes during output transitions. This minimizes the need for the large decoupling
capacitors required by the NE556.
These devices have internal electrostatic-discharge (ESD) protection circuits that prevent catastrophic failures
at voltages up to 2000 V as tested under MIL-STD-883C, Method 3015. However, care should be exercised in
handling these devices, as exposure to ESD may result in degradation of the device parametric performance.
All unused inputs should be tied to an appropriate logic level to prevent false triggering.
The TLC556C is characterized for operation from 0°C to 70°C. The TLC556I is characterized for operation from
– 40°C to 85°C. The TLC556M is characterized for operation over the full military temperature range of – 55°C
to 125°C.
LinCMOS is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright © 1997, Texas Instruments Incorporated
1

TLC556Y Datasheet
TLC556, TLC556Y
DUAL LinCMOSTIMERS
SLFS047B – FEBRUARY 1984 – REVISED SEPTEMBER 1997
AVAILABLE OPTIONS
TA
RANGE
VDD
RANGE
SMALL OUTLINE
(D)
PACKAGE
CHIP CARRIER
(FK)
CERAMIC DIP
(J)
PLASTIC DIP
(N)
O°C
to
70°C
2V
to
18 V
TLC556CD
TLC556CN
– 4O°C
to
85°C
3V
to
18 V
TLC556lD
TLC556IN
– 55°C
to
125°C
5V
to
18 V
TLC556MD
TLC556MFK
TLC556MJ
TLC556MN
The D package is available taped and reeled. Add the suffix R to the device type (e.g., TLC556CDR).
CHIP FORM
(Y)
TLC556Y
FUNCTION TABLE
RESET
VOLTAGE†
TRIGGER
VOLTAGE†
THRESHOLD
VOLTAGE†
OUTPUT
DISCHARGE
SWITCH
< MIN
Irrelevant
Irrelevant
L
On
> MAX
< MIN
Irrelevant
H
Off
>MAX
>MAX
>MAX
L
On
> MAX
> MAX
< MIN
As previously established
For conditions shown as MIN or MAX, use the appropriate value specified under electrical characteristics.
functional block diagram (each timer)
CONT
VDD 3
14
2
THRES
R
R
RESET
4
R1
R1
S
5
OUT
6
TRIG
R
7
GND
RESET can override TRIG and THRES.
TRIG can override THRES.
Pin numbers shown are for the D, J, or N packages.
1
DISCH
2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265


Features Datasheet pdf TLC556, TLC556Y DUAL LinCMOS™ TIMERS D Very Low Power Consumption . . . 2 mW Typ at VDD = 5 V D Capable of Operatio n in Astable Mode D CMOS Output Capable of Swinging Rail to Rail D High Output -Current Capability Sink 100 mA Typ Sou rce 10 mA Typ D Output Fully Compatible With CMOS, TTL, and MOS D Low Supply C urrent Reduces Spikes During Output Tra nsitions D Single-Supply Operation From 2 V to 15 V D Functionally interchange able With the NE556; Has Same Pinout S LFS047B – FEBRUARY 1984 – REVISED S EPTEMBER 1997 D, J, OR N PACKAGE (TOP V IEW) 1 DISCH 1 THRES 1 CONT 1 RESET 1 OUT 1 TRIG GND 1 2 3 4 5 6 7 14 VDD 1 3 2 DISCH 12 2 THRES 11 2 CONT 10 2 RES ET 9 2 OUT 8 2 TRIG FK PACKAGE (TOP VI EW) 1 THRES 1 DISCH NC VDD 2 DISCH de scription The TLC556 series are monolit hic timing circuits fabricated using th e TI LinCMOS™ process, which provides full compatibility with CMOS, TTL, and MOS logic and operates at frequencies up to 2 MHz. Accurate time delays and oscillations are possible with sm.
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