TIMER. TLC551Y Datasheet

TLC551Y Datasheet PDF


Part

TLC551Y

Description

TIMER

Manufacture

etcTI

Page 17 Pages
Datasheet
Download TLC551Y Datasheet


TLC551Y Datasheet
TLC551, TLC551Y
LinCMOSTIMERS
SLFS044B – FEBRUARY 1984 – REVISED SEPTEMBER 1997
D Very Low Power Consumption
1 mW Typ at VDD = 5 V
D Capable of Operation in Astable Mode
D CMOS Output Capable of Swinging Rail
to Rail
D High Output-Current Capability
D, DB, P, OR PW PACKAGE
(TOP VIEW)
GND
TRIG
OUT
RESET
1
2
3
4
8 VDD
7 DISCH
6 THRES
5 CONT
Sink 100 mA Typ
Source 10 mA Typ
functional block diagram
D Output Fully Compatible With CMOS, TTL,
and MOS
D Low Supply Current Reduces Spikes
During Output Transitions
D Single-Supply Operation From 1 V to 15 V
D Functionally Interchangeable With the
NE555; Has Same Pinout
CONT
VDD 5
8
R
6
THRES
R
RESET
4
R1
R1
S
3 OUT
D ESD Protection Exceeds 2000 V Per
TRIG 2
MIL-STD-883C, Method 3015.2
description
R
1
7
DISCH
The TLC551 is a monolithic timing circuit
fabricated using the TI LinCMOSprocess. The
GND
RESET can override TRIG, which can override THRES.
timer is fully compatible with CMOS, TTL, and MOS logic and operates at frequencies up to 2 MHz. Compared
to the NE555 timer, this device uses smaller timing capacitors because of its high input impedance. As a result,
more accurate time delays and oscillations are possible. Power consumption is low across the full range of
power supply voltage.
Like the NE555, the TLC551 has a trigger level equal to approximately one-third of the supply voltage and a
threshold level equal to approximately two-thirds of the supply voltage. These levels can be altered by use of
the control voltage terminal (CONT). When the trigger input (TRIG) falls below the trigger level, the flip-flop is
set and the output goes high. If TRIG is above the trigger level and the threshold input (THRES) is above the
threshold level, the flip-flop is reset and the output is low. The reset input (RESET) can override all other inputs
and can be used to initiate a new timing cycle. If RESET is low, the flip-flop is reset and the output is low.
Whenever the output is low, a low-impedance path is provided between DISCH and GND. All unused inputs
should be tied to an appropriate logic level to prevent false triggering.
While the CMOS output is capable of sinking over 100 mA and sourcing over 10 mA, the TLC551 exhibits greatly
reduced supply-current spikes during output transitions. This minimizes the need for the large decoupling
capacitors required by the NE555.
The TLC551C is characterized for operation from 0°C to 70°C.
This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These
circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C,
Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than maximum-rated
voltages to these high-impedance circuits. During storage or handling, the device leads should be shorted together or the device
should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriated logic voltage level,
preferably either supply voltage or ground. Specific guidelines for handling devices of this type are contained in the publication
Guidelines for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies available from Texas Instruments.
LinCMOS is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 1997, Texas Instruments Incorporated
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
1

TLC551Y Datasheet
TLC551, TLC551Y
LinCMOSTIMERS
SLFS044A – FEBRUARY 1984 – REVISED MAY 1997
AVAILABLE OPTIONS
PACKAGED DEVICES
TA
VDD
RANGE
SMALL
OUTLINE
(D)
SSOP
(DB)
PLASTIC DIP
(P)
TSSOP
(PW)
CHIP FORM
(Y)
0°C to 70°C 1 V to 16 V TLC551CD TLC551CDBLE TLC551CP TLC551CPWLE TLC551Y
The D package is available taped and reeled. Add the suffix R (e.g., TLC551CDR). The DB and PW packages are only
available left-end taped and reeled (indicated by the LE suffix on the device type; e.g., TLC551CDBLE). Chips are
tested at 25°C.
FUNCTION TABLE
RESET
VOLTAGE
TRIGGER THRESHOLD
VOLTAGE VOLTAGE
OUTPUT
DISCHARGE
SWITCH
<MIN
Irrelevant
Irrelevant
Low
On
>MAX
<MIN
Irrelevant
High
Off
>MAX
>MAX
>MAX
Low
On
>MAX
>MAX
<MIN
As previously established
For conditions shown as MIN or MAX, use the appropriate value specified under
electrical characteristics.
TLC551Y chip information
This chip, when properly assembled, displays characteristics similar to the TLC551. Thermal compression or
ultrasonic bonding may be used on the doped aluminum bonding pads. Chips may be mounted with conductive
epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
50
THRES
CONT
VDD (5)
(8)
R
(6)
R
RESET
(4)
R1
R1
S
(3)
OUT
(2)
TRIG
R
(1)
GND
(7)
DISCH
64 RESET can override TRIG, which can override THRES.
CHIP THICKNESS: 15 TYPICAL
BONDING PADS: 4 × 4 MINIMUM
TJmax = 150°C
TOLERANCES ARE ± 10%.
ALL DIMENSIONS ARE IN MILS.
PIN (1) IS INTERNALLY CONNECTED
TO BACKSIDE OF CHIP.
2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265


Features Datasheet pdf TLC551, TLC551Y LinCMOS™ TIMERS SLFS0 44B – FEBRUARY 1984 – REVISED SEPTE MBER 1997 D Very Low Power Consumption 1 mW Typ at VDD = 5 V D Capable of Ope ration in Astable Mode D CMOS Output Ca pable of Swinging Rail to Rail D High O utput-Current Capability D, DB, P, OR PW PACKAGE (TOP VIEW) GND TRIG OUT RES ET 1 2 3 4 8 VDD 7 DISCH 6 THRES 5 CO NT Sink 100 mA Typ Source 10 mA Typ f unctional block diagram D Output Fully Compatible With CMOS, TTL, and MOS D L ow Supply Current Reduces Spikes During Output Transitions D Single-Supply Ope ration From 1 V to 15 V D Functionally Interchangeable With the NE555; Has Sam e Pinout CONT VDD 5 8 R 6 THRES R RES ET 4 R1 R1 S 3 OUT D ESD Protection E xceeds 2000 V Per TRIG 2 MIL-STD-883C , Method 3015.2 description R 1 7 DIS CH The TLC551 is a monolithic timing c ircuit fabricated using the TI LinCMOS process. The GND RESET can override TRIG, which can override THRES. timer is fully compatible with CMOS, TTL, and MOS logic and operates at frequ.
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