(PDF) SN74HC86 Datasheet PDF | etcTI





SN74HC86 Datasheet PDF

Part Number SN74HC86
Description QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
Manufacture etcTI
Total Page 21 Pages
PDF Download Download SN74HC86 Datasheet PDF

Features: Datasheet pdf SN54HC86, SN74HC86 QUADRUPLE 2-INPUT EXC LUSIVE-OR GATES D Wide Operating Volta ge Range of 2 V to 6 V D Outputs Can Dr ive Up To 10 LSTTL Loads D Low Power Co nsumption, 20-µA Max ICC D Typical tpd = 10 ns SN54HC86 . . . J OR W PACKAGE SN74HC86 . . . D, N, NS, OR PW PACKAGE (TOP VIEW) SCLS100E – DECEMBER 1982 – REVISED AUGUST 2003 D ±4-mA Output Drive at 5 V D Low Input Current of 1 µA Max D True Logic SN54HC86 . . . FK PACKAGE (TOP VIEW) 1A 1B 1Y 2A 2B 2Y G ND 1 2 3 4 5 6 7 14 VCC 13 4B 12 4A 1 1 4Y 10 3B 9 3A 8 3Y 1Y 3 2 1 20 19 4 18 4A NC 5 17 NC 2A 6 16 4Y NC 7 15 NC 2B 8 14 3B 9 10 11 12 13 2Y 1B GND 1A NC NC 3Y VCC 3A 4B descript ion/ordering information NC – No int ernal connection ęThese devices conta in four independent 2-input exclusive-O R gates. They perform the Boolean funct ion Y = A B or Y = AB + AB in positive logic. A common application is as a tru e / complement element. If one of the i nputs is low, the other input is reproduced in true form at the output. I.

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SN74HC86 datasheet
SN54HC86, SN74HC86
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
D Wide Operating Voltage Range of 2 V to 6 V
D Outputs Can Drive Up To 10 LSTTL Loads
D Low Power Consumption, 20-µA Max ICC
D Typical tpd = 10 ns
SN54HC86 . . . J OR W PACKAGE
SN74HC86 . . . D, N, NS, OR PW PACKAGE
(TOP VIEW)
SCLS100E – DECEMBER 1982 – REVISED AUGUST 2003
D ±4-mA Output Drive at 5 V
D Low Input Current of 1 µA Max
D True Logic
SN54HC86 . . . FK PACKAGE
(TOP VIEW)
1A
1B
1Y
2A
2B
2Y
GND
1
2
3
4
5
6
7
14 VCC
13 4B
12 4A
11 4Y
10 3B
9 3A
8 3Y
1Y
3 2 1 20 19
4 18
4A
NC 5
17 NC
2A 6
16 4Y
NC 7
15 NC
2B 8
14 3B
9 10 11 12 13
description/ordering information
NC – No internal connection
ęThese devices contain four independent 2-input exclusive-OR gates. They perform the Boolean function
Y = A B or Y = AB + AB in positive logic.
A common application is as a true / complement element. If one of the inputs is low, the other input is reproduced
in true form at the output. If one of the inputs is high, the signal on the other input is reproduced inverted at the
output.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP – N
Tube of 25
SN74HC86N
SN74HC86N
Tube of 50
SN74HC86D
SOIC – D
Reel of 2500 SN74HC86DR
HC86
–40°C to 85°C
SOP – NS
Reel of 250
Reel of 2000
SN74HC86DT
SN74HC86NSR
HC86
Tube of 90
SN74HC86PW
TSSOP – PW
Reel of 2000 SN74HC86PWR
HC86
Reel of 250
SN74HC86PWT
CDIP – J
Tube of 25
SNJ54HC86J
SNJ54HC86J
–55°C to 125°C CFP – W
Tube of 150
SNJ54HC86W
SNJ54HC86W
LCCC – FK
Tube of 55
SNJ54HC86FK
SNJ54HC86FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 2003, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
1

SN74HC86 datasheet
SN54HC86, SN74HC86
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
SCLS100E – DECEMBER 1982 – REVISED AUGUST 2003
FUNCTION TABLE
(each gate)
INPUTS
AB
LL
LH
OUTPUT
Y
L
H
HL
H
HH
L
exclusive-OR logic
An exclusive-OR gate has many applications, some of which can be represented better by alternative logic
symbols.
Exclusive OR
=1
These are five equivalent exclusive-OR symbols valid for an ’HC86 gate in positive logic; negation may be
shown at any two ports.
Logic Identity Element
Even-Parity Element
Odd-Parity Element
= 2k 2k + 1
The output is active (low) if
all inputs stand at the same
logic level (i.e., A = B).
The output is active (low) if
an even number of inputs
(i.e., 0 or 2) are active.
The output is active (high) if
an odd number of inputs (i.e.,
only 1 of the 2) are active.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265




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