(PDF) UC1715-SP Datasheet PDF | etcTI





UC1715-SP Datasheet PDF

Part Number UC1715-SP
Description COMPLIMENTARY SWITCH FET DRIVERS
Manufacture etcTI
Total Page 14 Pages
PDF Download Download UC1715-SP Datasheet PDF

Features: Datasheet pdf UC1715-SP www.ti.com COMPLIMENTARY SWI TCH FET DRIVERS Check for Samples: UC17 15-SP FEATURES 1 • Single Input (PWM and TTL Compatible) • High Current P ower FET Driver, 1-A Source/2-A Sink Auxiliary Output FET Driver, 0.5-A So urce/1-A Sink • Time Delays Between P ower and Auxiliary Outputs Independentl y Programmable from 50 ns to 700 ns • Time Delay or True Zero-Voltage Operat ion Independently Configurable for Each Output • Switching Frequency to 1 MH z • Typical 50-ns Propagation Delays • ENBL Pin Activates 220-μA Sleep Mo de • Power Output is Active Low in Sl eep Mode • Synchronous Rectifier Driv er XXX XXX W PACKAGE (TOP VIEW) SLUSA U8 – MAY 2013 DESCRIPTION The UC1715 is a high speed driver designed to pro vide drive waveforms for complementary switches. Complementary switch configur ations are commonly used in synchronous rectification circuits and active clam p/reset circuits, which can provide zer o voltage switching. In order to facilitate the soft switching transitions, independen.

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UC1715-SP datasheet
UC1715-SP
www.ti.com
COMPLIMENTARY SWITCH FET DRIVERS
Check for Samples: UC1715-SP
FEATURES
1
• Single Input (PWM and TTL Compatible)
• High Current Power FET Driver,
1-A Source/2-A Sink
• Auxiliary Output FET Driver,
0.5-A Source/1-A Sink
• Time Delays Between Power and Auxiliary
Outputs Independently Programmable from
50 ns to 700 ns
• Time Delay or True Zero-Voltage Operation
Independently Configurable for Each Output
• Switching Frequency to 1 MHz
• Typical 50-ns Propagation Delays
• ENBL Pin Activates 220-μA Sleep Mode
• Power Output is Active Low in Sleep Mode
• Synchronous Rectifier Driver
XXX
XXX
W PACKAGE
(TOP VIEW)
SLUSAU8 – MAY 2013
DESCRIPTION
The UC1715 is a high speed driver designed to provide drive waveforms for complementary switches.
Complementary switch configurations are commonly used in synchronous rectification circuits and active
clamp/reset circuits, which can provide zero voltage switching. In order to facilitate the soft switching transitions,
independently programmable delays between the two output waveforms are provided on this driver. The delay
pins also have true zero voltage sensing capability which allows immediate activation of the corresponding switch
when zero voltage is applied. This device requires a PWM-type input to operate and can be interfaced with
commonly available PWM controllers.
TJ
–55°C to 125°C
ORDERING INFORMATION(1)
PACKAGE
ORDERABLE PART NUMBER
CFP (W)
5962-0052102VFA
TOP-SIDE MARKING
5962-0052102VFA
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated

UC1715-SP datasheet
UC1715-SP
SLUSAU8 – MAY 2013
DEVICE INFORMATION
www.ti.com
PIN
NAME
NO.
1, 7, 8,
N/C 9, 10,
12, 13
VCC
2
PWR
3
GND
AUX
4, 5
6
T2 11
INPUT
14
T1 15
ENBL
16
I/O DESCRIPTION
PIN FUNCTIONS
- N/C pins are not bonded out. External connections will not affect device functionality.
I
The VCC input range is from 7 V to 20 V. This pin should be bypassed with a capacitor to GND consistent with
peak load current demands.
The PWR output waits for the T1 delay after the INPUT’s rising edge before switching on, but switches off
O
immediately at INPUT’s falling edge (neglecting propagation delays). This output is capable of sourcing 1-A
and sinking 2-A of peak gate drive current. PWR output includes a passive, self-biased circuit which holds this
pin active low, when ENBL 0.8 V regardless of VCC’s voltage.
This is the reference pin for all input voltages and the return point for all device currents. It carries the full
- peak sinking current from the outputs. Any tendency for the outputs to ring below GND voltage must be
damped or clamped such that GND remains the most negative potential.
The AUX switches immediately at INPUT’s rising edge but waits through the T2 delay after INPUT’s falling
edge before switching. AUX is capable of sourcing 0.5-A and sinking 1-A of drive current. During sleep mode,
AUX is inactive with a high impedance.
This pin functions in the same way as T1 but controls the time delay between PWR turn-off and activation of
the AUX switch.
The resistor on this pin sets the charging current on internal timing capacitors to provide independent time
control. The nominal voltage level at this pin is 3 V and the current is internally limited to 1 mA. The total delay
from INPUT to output includes a propagation delay in addition to the programmable timer but since the
propagation delays are approximately equal, the relative time delay between the two outputs can be assumed
to be solely a function of the programmed delays. The relationship of the time delay vs. RT is shown in the
Typical Characteristics curves.
The input switches at TTL logic levels (approximately 1.4 V) but the allowable range is from 0 V to 20 V,
allowing direct connection to most common IC PWM controller outputs. The rising edge immediately switches
the AUX output, and initiates a timing delay, T1, before switching on the PWR output. Similarly, the INPUT
I
falling edge immediately turns off the PWR output and initiates a timing delay, T2, before switching the AUX
output.
It should be noted that if the input signal comes from a controller with FET drive capability, this signal provides
another option. INPUT and PWR provide a delay only at the leading edge while INPUT and AUX provide the
delay at the trailing edge.
A resistor to ground programs the time delay between AUX switch turn-off and PWR turn-on.
The resistor on this pin sets the charging current on internal timing capacitors to provide independent time
control. The nominal voltage level at this pin is 3 V and the current is internally limited to 1 mA. The total delay
from INPUT to output includes a propagation delay in addition to the programmable timer but since the
propagation delays are approximately equal, the relative time delay between the two outputs can be assumed
to be solely a function of the programmed delays. The relationship of the time delay vs. RT is shown in the
Typical Characteristics curves.
The ENBL input switches at TTL logic levels (approximately 1.2 V), and its input range is from 0 V to 20 V.
I The ENBL input will place the device into sleep mode when it is a logical low. The current into VCC during the
sleep mode is typically 220 μA.
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Product Folder Links: UC1715-SP
Copyright © 2013, Texas Instruments Incorporated




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