CONTROLLER. UC2823A Datasheet

UC2823A Datasheet PDF


Part

UC2823A

Description

HIGH-SPEED PWM CONTROLLER

Manufacture

etcTI

Page 18 Pages
Datasheet
Download UC2823A Datasheet


UC2823A Datasheet
www.ti.com
UC1823A, UC2823A, UC2823B,
UC3823A, UC3823B, UC1825A,
UC2825A, UC2825B, UC3825A, UC3825B
SLUS334E AUGUST 1995 REVISED SEPTEMBER 2010
HIGH-SPEED PWM CONTROLLER
FEATURES
D Improved Versions of the UC3823/UC3825
PWMs
D Compatible with Voltage-Mode or
Current-Mode Control Methods
D Practical Operation at Switching Frequencies
to 1 MHz
D 50-ns Propagation Delay to Output
D High-Current Dual Totem Pole Outputs
(2-A Peak)
D Trimmed Oscillator Discharge Current
D Low 100-μA Startup Current
D Pulse-by-Pulse Current Limiting Comparator
D Latched Overcurrent Comparator With Full
Cycle Restart
BLOCK DIAGRAM
DESCRIPTION
The UC3823A and UC3823B and the UC3825A and
UC3825B family of PWM controllers are improved
versions of the standard UC3823 and UC3825 family.
Performance enhancements have been made to several
of the circuit blocks. Error amplifier gain bandwidth product
is 12 MHz, while input offset voltage is 2 mV. Current limit
threshold is assured to a tolerance of 5%. Oscillator
discharge current is specified at 10 mA for accurate dead
time control. Frequency accuracy is improved to 6%.
Startup supply current, typically 100 μA, is ideal for off-line
applications. The output drivers are redesigned to actively
sink current during UVLO at no expense to the startup
current specification. In addition each output is capable of
2-A peak currents during transitions.
CLK/LEB 4
RT 5
CT 6
RAMP 7
EAOUT 3
NI 2
INV 1
SS 8
ILIM 9
VCC 15
GND 10
OSC
(60%)
1.25 V
PWM COMPARATOR
R
SD
PWM
LATCH
*
T
E/A
9 mA
1.0 V
1.2 V
0.2 V
”B” 16V/10V
”A” 9.2V/8.4V
CURRENT
LIMIT
5V
OVER CURRENT
SD
RESTART
DELAY
R
FAULT LATCH
UVLO
VREF
5.1 V
ON/OFF
4V
SOFTSTART COMPLETE
RESTART
DELAY
LATCH
S
R
250 mA
VREF GOOD
INTERNAL
BIAS
* On the UC1823A version, toggles Q and Q are always low.
13 VC
11 OUTA
14 OUTB
12 PGND
16 5.1 VREF
UDG02091
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
Copyright © 2004 2008, Texas Instruments Incorporated

UC2823A Datasheet
UC1823A, UC2823A, UC2823B,
UC3823A, UC3823B, UC1825A,
UC2825A, UC2825B, UC3825A, UC3825B
SLUS334E AUGUST 1995 REVISED SEPTEMBER 2010
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION (CONTINUED)
Functional improvements have also been implemented in this family. The UC3825 shutdown comparator is now a
high-speed overcurrent comparator with a threshold of 1.2 V. The overcurrent comparator sets a latch that ensures full
discharge of the soft-start capacitor before allowing a restart. While the fault latch is set, the outputs are in the low state.
In the event of continuous faults, the soft-start capacitor is fully charged before discharge to insure that the fault frequency
does not exceed the designed soft start period. The UC3825 CLOCK pin has become CLK/LEB. This pin combines the
functions of clock output and leading edge blanking adjustment and has been buffered for easier interfacing.
The UC3825A and UC3825B have dual alternating outputs and the same pin configuration of the UC3825. The UC3823A
and UC3823B outputs operate in phase with duty cycles from zero to less than 100%. The pin configuration of the UC3823A
and UC3823B is the same as the UC3823 except pin 11 is now an output pin instead of the reference pin to the current
limit comparator. “A” version parts have UVLO thresholds identical to the original UC3823 and UC3825. The “B” versions
have UVLO thresholds of 16 V and 10 V, intended for ease of use in off-line applications.
Consult the application note, The UC3823A,B and UC3825A,B Enhanced Generation of PWM Controllers, (SLUA125) for
detailed technical and applications information.
ORDERING INFORMATION
UVLO
TA
MAXIMUM
DUTY CYCLE
SOIC16(1)
9.2 V / 8.4 V
PDIP16
PLCC20(1)
SOIC16
16 V / 10 V
PDIP16
PLCC20(1)
(DW)
(N)
(Q) (DW) (N)
(Q)
40°C to 85°C
< 100%
< 50%
UC2823ADW
UC2825ADW
UC2823AN
UC2825AN
UC2823AQ
UC2825AQ
UC2823BDW
UC2825BDW
UC2823BN
UC2825BN
0°C to 70°C
< 100%
< 50%
UC3823ADW
UC3825ADW
UC3823AN
UC3825AN
UC3823AQ
UC3825AQ
UC3823BDW
UC3825BDW
UC3823BN
UC3825BN
UC3825BQ
(1) The DW and Q packages are also available taped and reeled. Add TR suffix to the device type (i.e., UC2823ADWR). To order quantities of 1000
devices per reel for the Q package and 2000 devices per reel for the DW package.
TA
MAXIMUM
DUTY CYCLE
55°C to 125°C
< 100%
< 50%
UVLO
9.2 V / 8.4 V
CDIP16
(J)
LCCC20
(L)
UC1823AJ, UC1823AJ883B, UC1823AJQMLV
UC1823AL, UC1823AL883B
UC1825AJ, UC1825AJ883B, UC1825AJQMLV
UC1825AL, UC1825AL883B, UC1825ALQMLV
PIN ASSIGNMENTS
DW, J, OR N PACKAGES
(TOP VIEW)
Q OR L PACKAGES
(TOP VIEW)
INV
NI
EAOUT
CLK/LEB
RT
CT
RAMP
SS
1
2
3
4
5
6
7
8
16 VREF
15 VCC
14 OUTB
13 VC
12 PGND
11 OUTA
10 GND
9 ILIM
EAOUT
CLK/LEB
NC
RT
CT
3 2 1 20 19
4 18
5 17
6 16
7 15
89
14
10 11 12 13
OUTB
VC
NC
PGND
OUTA
NC = no connection
2


Features Datasheet pdf www.ti.com UC1823A, UC2823A, UC2823B, U C3823A, UC3823B, UC1825A, UC2825A, UC28 25B, UC3825A, UC3825B SLUS334E − AUGU ST 1995 − REVISED SEPTEMBER 2010 HIGH -SPEED PWM CONTROLLER FEATURES D Impro ved Versions of the UC3823/UC3825 PWMs D Compatible with Voltage-Mode or Curre nt-Mode Control Methods D Practical Ope ration at Switching Frequencies to 1 MH z D 50-ns Propagation Delay to Output D High-Current Dual Totem Pole Outputs ( 2-A Peak) D Trimmed Oscillator Discharg e Current D Low 100-μA Startup Current D Pulse-by-Pulse Current Limiting Comp arator D Latched Overcurrent Comparator With Full Cycle Restart BLOCK DIAGRAM DESCRIPTION The UC3823A and UC3823B an d the UC3825A and UC3825B family of PWM controllers are improved versions of t he standard UC3823 and UC3825 family. P erformance enhancements have been made to several of the circuit blocks. Error amplifier gain bandwidth product is 12 MHz, while input offset voltage is 2 m V. Current limit threshold is assured to a tolerance of 5%. Oscillat.
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