UC3823B Datasheet PDF


Part Number

UC3823B

Description

HIGH-SPEED PWM CONTROLLER

Manufacture

etcTI

Total Page 18 Pages
PDF Download
Download UC3823B Datasheet PDF


Features Datasheet pdf www.ti.com UC1823A, UC2823A, UC2823B, U C3823A, UC3823B, UC1825A, UC2825A, UC28 25B, UC3825A, UC3825B SLUS334E − AUGU ST 1995 − REVISED SEPTEMBER 2010 HIGH -SPEED PWM CONTROLLER FEATURES D Impro ved Versions of the UC3823/UC3825 PWMs D Compatible with Voltage-Mode or Curre nt-Mode Control Methods D Practical Ope ration at Switching Frequencies to 1 MH z D 50-ns Propagation Delay to Output D High-Current Dual Totem Pole Outputs ( 2-A Peak) D Trimmed Oscillator Discharg e Current D Low 100-μA Startup Current D Pulse-by-Pulse Current Limiting Comp arator D Latched Overcurrent Comparator With Full Cycle Restart BLOCK DIAGRAM DESCRIPTION The UC3823A and UC3823B an d the UC3825A and UC3825B family of PWM c.
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UC3823B Datasheet
www.ti.com
UC1823A, UC2823A, UC2823B,
UC3823A, UC3823B, UC1825A,
UC2825A, UC2825B, UC3825A, UC3825B
SLUS334E AUGUST 1995 REVISED SEPTEMBER 2010
HIGH-SPEED PWM CONTROLLER
FEATURES
D Improved Versions of the UC3823/UC3825
PWMs
D Compatible with Voltage-Mode or
Current-Mode Control Methods
D Practical Operation at Switching Frequencies
to 1 MHz
D 50-ns Propagation Delay to Output
D High-Current Dual Totem Pole Outputs
(2-A Peak)
D Trimmed Oscillator Discharge Current
D Low 100-μA Startup Current
D Pulse-by-Pulse Current Limiting Comparator
D Latched Overcurrent Comparator With Full
Cycle Restart
BLOCK DIAGRAM
DESCRIPTION
The UC3823A and UC3823B and the UC3825A and
UC3825B family of PWM controllers are improved
versions of the standard UC3823 and UC3825 family.
Performance enhancements have been made to several
of the circuit blocks. Error amplifier gain bandwidth product
is 12 MHz, while input offset voltage is 2 mV. Current limit
threshold is assured to a tolerance of 5%. Oscillator
discharge current is specified at 10 mA for accurate dead
time control. Frequency accuracy is improved to 6%.
Startup supply current, typically 100 μA, is ideal for off-line
applications. The output drivers are redesigned to actively
sink current during UVLO at no expense to the startup
current specification. In addition each output is capable of
2-A peak currents during transitions.
CLK/LEB 4
RT 5
CT 6
RAMP 7
EAOUT 3
NI 2
INV 1
SS 8
ILIM 9
VCC 15
GND 10
OSC
(60%)
1.25 V
PWM COMPARATOR
R
SD
PWM
LATCH
*
T
E/A
9 mA
1.0 V
1.2 V
0.2 V
”B” 16V/10V
”A” 9.2V/8.4V
CURRENT
LIMIT
5V
OVER CURRENT
SD
RESTART
DELAY
R
FAULT LATCH
UVLO
VREF
5.1 V
ON/OFF
4V
SOFTSTART COMPLETE
RESTART
DELAY
LATCH
S
R
250 mA
VREF GOOD
INTERNAL
BIAS
* On the UC1823A version, toggles Q and Q are always low.
13 VC
11 OUTA
14 OUTB
12 PGND
16 5.1 VREF
UDG02091
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
Copyright © 2004 2008, Texas Instruments Incorporated




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