Dual J-K Flip-Flop
Data sheet acquired from Harris Semiconductor SCHS141H
March 1998 - Revised October 2003
CD54HC112, CD74HC112, CD54HCT1...
Description
Data sheet acquired from Harris Semiconductor SCHS141H
March 1998 - Revised October 2003
CD54HC112, CD74HC112, CD54HCT112, CD74HCT112
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger
[ /Title (CD74 HC112 , CD74 HCT11 2) /Subject (Dual J-K FlipFlop with Set and Reset Nega-
Features
Description
Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times
Asynchronous Set and Reset
Complementary Outputs
Buffered Inputs
TTAyp=ic2a5lofCMAX = 60MHz at VCC = 5V, CL = 15pF, Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads Wide Operating Temperature Range . . . -55oC to 125oC
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to LSTTL Logic ICs
HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
Pinout
CD54HC112, CD54HCT112 (CERDIP) CD74HC112 (PDIP, SOIC, SOP, TSSOP)
CD74HCT112 (PDIP) TOP VIEW
The ’HC112 and ’HCT112 utilize silicon-gate CMOS technology to achieve operating speeds equivalent to LSTTL parts. They exhibit the low power consumption of standard CMOS integrated circuits, together with the ability to drive 10 LSTTL loads.
These flip-flops have independent J, K, Set, Rese...
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