CD74HCT107

Data sheet acquired from Harris Semiconductor SCHS139D March 1998 - Revised October 2003 CD54HC107, CD74HC107, CD74HCT107 Dual J-K Flip-Flop with Reset Negative-Edge Trigger [ /Title (CD74 HC107 , CD74 HCT10 7) /Subject (Dual J-K FlipFlop with Reset Negative- Features Description Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times Asynchronous Reset Complementary Outputs Buffered Inputs TTAyp=ic2a5lofCMAX = 60MHz at VCC = 5V, CL = 15pF, Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads Wide Operating Temperature Range . . . -55oC to 125oC The ’HC107 and CD74HCT107 utilize silicon gate CMOS technology to achieve operating speeds equivalent to LSTTL parts. They exhibit the low power consumption of standard CMOS integrated circuits, together with the ability to drive 10 LSTTL loads. These flip-flops have independent J, K, Reset and Clock inputs and Q and Q outputs. They change state on the negative-going transition of the clock pulse. Reset is accomplished asynchronously by a low level input. This device is functionally identical to the HC/HCT73 but differs in terminal assignment and in some parametric limits. The HCT logic family is functionally as well as pin compatible with the standard LS family. Balanced Propagation Delay and Transition Times Significant Power Reduction Compared to LSTTL Logic ICs HC T...