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CD74HC109 Dataheets PDF



Part Number CD74HC109
Manufacturers Texas Instruments
Logo Texas Instruments
Description Dual J-K Flip-Flop
Datasheet CD74HC109 DatasheetCD74HC109 Datasheet (PDF)

Data sheet acquired from Harris Semiconductor SCHS140E March 1998 - Revised October 2003 CD54HC109, CD74HC109, CD54HCT109, CD74HCT109 Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger [ /Title (CD74H C109, CD74H CT109) /Subject (Dual JK FlipFlop with Set and Reset Features Description • Asynchronous Set and Reset • Schmitt Trigger Clock Inputs • TTAyp=ic2a5lofCMAX = 54MHz at VCC = 5V, CL = 15pF, • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 .

  CD74HC109   CD74HC109


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Data sheet acquired from Harris Semiconductor SCHS140E March 1998 - Revised October 2003 CD54HC109, CD74HC109, CD54HCT109, CD74HCT109 Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger [ /Title (CD74H C109, CD74H CT109) /Subject (Dual JK FlipFlop with Set and Reset Features Description • Asynchronous Set and Reset • Schmitt Trigger Clock Inputs • TTAyp=ic2a5lofCMAX = 54MHz at VCC = 5V, CL = 15pF, • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads • Wide Operating Temperature Range . . . -55oC to 125oC The ’HC109 and ’HCT109 are dual J-K flip-flops with set and reset. The flip-flop changes state with the positive transition of Clock (1CP and 2CP). The flip-flop is set and reset by active-low S and R, respectively. A low on both the set and reset inputs simultaneously will force both Q and Q outputs high. However, both set and reset going high simultaneously results in an unpredictable output condition. Ordering Information • Balanced Propagation Delay and Transition Times • Significant Power Reduction Compared to LSTTL Logic ICs • HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V • HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH Pinout CD54HC109, CD54HCT109 (CERDIP) CD74HC109, CD74HCT109 (PDIP, SOIC) TOP VIEW PART NUMBER TEMP. RANGE (oC) PACKAGE CD54HC109F3A -55 to 125 16 Ld CERDIP CD54HCT109F3A -55 to 125 16 Ld CERDIP CD74HC109E -55 to 125 16 Ld PDIP CD74HC109M -55 to 125 16 Ld SOIC CD74HC109MT -55 to 125 16 Ld SOIC CD74HC109M96 -55 to 125 16 Ld SOIC CD74HCT109E -55 to 125 16 Ld PDIP CD74HCT109M -55 to 125 16 Ld SOIC CD74HCT109MT -55 to 125 16 Ld SOIC CD74HCT109M96 -55 to 125 16 Ld SOIC NOTE: When ordering, use the entire part number. The suffix 96 denotes tape and reel. The suffix T denotes a small-quantity reel of 250. 1R 1 1J 2 1K 3 1CP 4 1S 5 1Q 6 1Q 7 GND 8 16 VCC 15 2R 14 2J 13 2K 12 2CP 11 2S 10 2Q 9 2Q CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, Texas Instruments Incorporated 1 CD54HC109, CD74HC109, CD54HCT109, CD74HCT109 Functional Diagram 5 1S 1J 1K 1CP 1R 2 3 4 1 F/F 1 6 1Q 7 1Q 11 2S 14 2J 13 2K 12 2CP 15 2R F/F 2 10 2Q 9 2Q GND = 8 VCC = 16 TRUTH TABLE INPUTS S R CP J LHXX HLXX L LXX HH↑ L HH↑H HH↑ L HH↑H HHL X H= High Level (Steady State) L= Low Level (Steady State) X= Don’t Care ↑= Low-to-High Transition NOTE: 1. Unpredictable and unstable condition if both S and R go high simultaneously K X X X L L H H X OUTPUTS QQ HL LH H (Note 1) H (Note 1) LH Toggle No Change HL No Change Logic Diagram 5(11) S 2(14) J 3(13) K 4(12) CP 1(15) R 16 VCC 8 GND JS K CL FF CL Q RQ 6(10) Q 7(9) Q 2 CD54HC109, CD74HC109, CD54HCT109, CD74HCT109 Absolute Maximum Ratings DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Drain Current, per Output, IO For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA Thermal Information Thermal Resistance (Typical, Note 2) θJA (oC/W) E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . 67 M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . 73 Maximum Junction Temperature (Hermetic Package or Die) . . . 175oC Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC CP Input Rise and Fall Time, tr, tf 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0ms (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0ms (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0ms (Max) Input Rise and Fall Time (All Inputs .


CD54HC109 CD74HC109 CD54HCT109


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