Registers. SN74HC165-Q1 Datasheet

SN74HC165-Q1 Datasheet PDF


Part

SN74HC165-Q1

Description

8-Bit Parallel-Load Shift Registers

Manufacture

etcTI

Page 18 Pages
Datasheet
Download SN74HC165-Q1 Datasheet


SN74HC165-Q1 Datasheet
SN74HC165ĆQ1
8ĆBIT PARALLELĆLOAD SHIFT REGISTER
D Qualified for Automotive Applications
D ESD Protection Exceeds 1500 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D Wide Operating Voltage Range of 2 V to 6 V
D Outputs Can Drive Up To 10 LSTTL Loads
D Low Power Consumption, 80-µA Max ICC
D Typical tpd = 13 ns
D ±4-mA Output Drive at 5 V
D Low Input Current of 1 µA Max
D Complementary Outputs
D Direct Overriding Load (Data) Inputs
D Gated Clock Inputs
D Parallel-to-Serial Data Conversion
SCLS518A − AUGUST 2003 − REVISED APRIL 2008
D OR PW PACKAGE
(TOP VIEW)
SH/LD
CLK
E
F
G
H
QH
GND
1
2
3
4
5
6
7
8
16 VCC
15 CLK INH
14 D
13 C
12 B
11 A
10 SER
9 QH
description/ordering information
The SN74HC165 is an 8-bit parallel-load shift register that, when clocked, shift the data toward a serial (QH)
output. Parallel-in access to each stage is provided by eight individual direct data (A−H) inputs that are enabled
by a low level at the shift/load (SH/LD) input. The SN74HC165 also features a clock-inhibit (CLK INH) function
and a complementary serial (QH) output.
Clocking is accomplished by a low-to-high transition of the clock (CLK) input while SH/LD is held high and CLK
INH is held low. The functions of CLK and CLK INH are interchangeable. Since a low CLK and a low-to-high
transition of CLK INH also accomplish clocking, CLK INH should be changed to the high level only while CLK
is high. Parallel loading is inhibited when SH/LD is held high. While SH/LD is low, the parallel inputs to the
register are enabled independently of the levels of the CLK, CLK INH, or serial (SER) inputs.
ORDERING INFORMATION{
TA
PACKAGE‡
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
SOIC − D
−40°C to 125°C
TSSOP − PW
Tape and reel
Tape and reel
SN74HC165QDRQ1
SN74HC165QPWRQ1
HC165Q1
HC165Q1
For the most current package and ordering information, see the Package Option Addendum at the end of this
document, or see the TI web site at http://www.ti.com.
Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 2008, Texas Instruments Incorporated
1

SN74HC165-Q1 Datasheet
SN74HC165ĆQ1
8ĆBIT PARALLELĆLOAD SHIFT REGISTER
SCLS518A − AUGUST 2003 − REVISED APRIL 2008
FUNCTION TABLE
INPUTS
FUNCTION
SH/LD CLK CLK INH
LX
X Parallel load
HH
X No change
HX
H No change
HL
Shift†
H
L
Shift†
Shift = content of each internal register shifts
toward serial output QH. Data at SER is
shifted into the first register.
logic diagram (positive logic)
SH/LD 1
A BC D E F GH
11 12 13 14 3 4 5 6
CLK INH 15
CLK 2
SER 10
9 QH
S SS SS SSS
C1 C1 C1 C1 C1 C1 C1 C1
1D 1D 1D 1D 1D 1D 1D 1D
R RR RR RRR
7
QH
2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265


Features Datasheet pdf SN74HC165ĆQ1 8ĆBIT PARALLELĆLOAD SHIF T REGISTER D Qualified for Automotive Applications D ESD Protection Exceeds 1 500 V Per MIL-STD-883, Method 3015; Exc eeds 200 V Using Machine Model (C = 200 pF, R = 0) D Wide Operating Voltage Ra nge of 2 V to 6 V D Outputs Can Drive U p To 10 LSTTL Loads D Low Power Consump tion, 80-µA Max ICC D Typical tpd = 13 ns D ±4-mA Output Drive at 5 V D Low Input Current of 1 µA Max D Complement ary Outputs D Direct Overriding Load (D ata) Inputs D Gated Clock Inputs D Para llel-to-Serial Data Conversion SCLS518 A − AUGUST 2003 − REVISED APRIL 200 8 D OR PW PACKAGE (TOP VIEW) SH/LD CLK E F G H QH GND 1 2 3 4 5 6 7 8 16 VC C 15 CLK INH 14 D 13 C 12 B 11 A 10 SER 9 QH description/ordering information The SN74HC165 is an 8-bit parallel-lo ad shift register that, when clocked, s hift the data toward a serial (QH) outp ut. Parallel-in access to each stage is provided by eight individual direct da ta (A−H) inputs that are enabled by a low level at the shift/load (SH/LD).
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