Counter. SN74HC163-Q1 Datasheet

SN74HC163-Q1 Datasheet PDF


Part

SN74HC163-Q1

Description

4-Bit Synchronous Binary Counter

Manufacture

etcTI

Page 20 Pages
Datasheet
Download SN74HC163-Q1 Datasheet


SN74HC163-Q1 Datasheet
SN74HC163ĆQ1
4ĆBIT SYNCHRONOUS BINARY COUNTER
SCLS584A − MAY 2004 − REVISED APRIL 2008
D Qualified for Automotive Applications
D Carry Output for n-Bit Cascading
D Wide Operating Voltage Range of 2 V to 6 V
D Synchronous Counting
D Outputs Can Drive Up To 10 LSTTL Loads
D Synchronously Programmable
D Low Power Consumption, 80-µA Max ICC
D Typical tpd = 14 ns
D ±4-mA Output Drive at 5 V
PW PACKAGE
(TOP VIEW)
D Low Input Current of 1 µA Max
D Internal Look-Ahead for Fast Counting
description/ordering information
This synchronous, presettable counter features an
internal carry look-ahead for application in
high-speed counting designs. The SN74HC163 is a
4-bit binary counter. Synchronous operation is
CLR
CLK
A
B
C
D
ENP
GND
1
2
3
4
5
6
7
8
16 VCC
15 RCO
14 QA
13 QB
12 QC
11 QD
10 ENT
9 LOAD
provided by having all flip-flops clocked
simultaneously so that the outputs change coincident with each other when instructed by the count-enable
(ENP, ENT) inputs and internal gating. This mode of operation eliminates the output counting spikes normally
associated with synchronous (ripple-clock) counters. A buffered clock (CLK) input triggers the four flip-flops on
the rising (positive-going) edge of the clock waveform.
This counter is fully programmable; that is, it can be preset to any number between 0 and 9 or 15. As presetting
is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree
with the setup data after the next clock pulse, regardless of the levels of the enable inputs.
The clear function for the SN74HC163 is synchronous. A low level at the clear (CLR) input sets all four of the
flip-flop outputs low after the next low-to-high transition of CLK, regardless of the levels of the enable inputs.
This synchronous clear allows the count length to be modified easily by decoding the Q outputs for the maximum
count desired. The active-low output of the gate used for decoding is connected to CLR to synchronously clear
the counter to 0000 (LLLL).
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without
additional gating. ENP, ENT, and a ripple-carry output (RCO) are instrumental in accomplishing this function.
Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. Enabling RCO produces a
high-level pulse while the count is maximum (9 or 15 with QA high). This high-level overflow ripple-carry pulse
can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the
level of CLK.
ORDERING INFORMATION{
TA
PACKAGE‡
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
−40°C to 85°C TSSOP − PW
Tape and reel SN74HC163IPWRQ1 HC163I
For the most current package and ordering information, see the Package Option Addendum at the end of this
document, or see the TI web site at http://www.ti.com.
Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 2008 Texas Instruments Incorporated
1

SN74HC163-Q1 Datasheet
SN74HC163ĆQ1
4ĆBIT SYNCHRONOUS BINARY COUNTER
SCLS584A − MAY 2004 − REVISED APRIL 2008
description/ordering information (continued)
This counter features a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that
modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of
the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the
stable setup and hold times.
logic diagram (positive logic)
LOAD 9
ENT 10
ENP 7
CLK
CLR
2
1
LD†
CK†
CK LD
R
15
RCO
3
A
4
B
M1
G2
1, 2T/1C3
G4
3D
4R
M1
G2
1, 2T/1C3
G4
3D
4R
14
QA
13
QB
C5
M1
G2
1, 2T/1C3
G4
3D
4R
12
QC
6
D
M1
G2
1, 2T/1C3
G4
3D
4R
11
QD
For simplicity, routing of complementary signals LD and CK is not shown on this overall logic diagram. The uses of these signals are shown
on the logic diagram of the D/T flip-flops.
2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265


Features Datasheet pdf SN74HC163ĆQ1 4ĆBIT SYNCHRONOUS BINARY COUNTER SCLS584A − MAY 2004 − REVI SED APRIL 2008 D Qualified for Automot ive Applications D Carry Output for n- Bit Cascading D Wide Operating Voltage Range of 2 V to 6 V D Synchronous Cou nting D Outputs Can Drive Up To 10 LST TL Loads D Synchronously Programmable D Low Power Consumption, 80-µA Max IC C D Typical tpd = 14 ns D ±4-mA Output Drive at 5 V PW PACKAGE (TOP VIEW) D Low Input Current of 1 µA Max D Inter nal Look-Ahead for Fast Counting descri ption/ordering information This synchro nous, presettable counter features an i nternal carry look-ahead for applicatio n in high-speed counting designs. The S N74HC163 is a 4-bit binary counter. Syn chronous operation is CLR CLK A B C D ENP GND 1 2 3 4 5 6 7 8 16 VCC 15 RCO 14 QA 13 QB 12 QC 11 QD 10 ENT 9 LOAD provided by having all flip-flops cloc ked simultaneously so that the outputs change coincident with each other when instructed by the count-enable (ENP, ENT) inputs and internal gating. .
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