REGISTER. SN74HC166A-Q1 Datasheet

SN74HC166A-Q1 Datasheet PDF


Part

SN74HC166A-Q1

Description

8-BIT PARALLEL-LOAD SHIFT REGISTER

Manufacture

etcTI

Page 17 Pages
Datasheet
Download SN74HC166A-Q1 Datasheet


SN74HC166A-Q1 Datasheet
SN74HC166AĆQ1
8ĆBIT PARALLELĆLOAD SHIFT REGISTER
SCLS538A − AUGUST 2003 − REVISED APRIL 2008
D Qualified for Automotive Applications
D Low Input Current of 1 µA Max
D ESD Protection Exceeds 2000 V Per
D Synchronous Load
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D Wide Operating Voltage Range of 2 V to 6 V
D Direct Overriding Clear
D Parallel-to-Serial Conversion
D Outputs Can Drive Up To 10 LSTTL Loads
D Low Power Consumption, 80-µA Max ICC
D Typical tpd = 13 ns
D ±4-mA Output Drive at 5 V
D OR PW PACKAGE
(TOP VIEW)
SER
A
B
1
2
3
16 VCC
15 SH/LD
14 H
description/ordering information
This parallel-in or serial-in, serial-out register
features gated clock (CLK, CLK INH) inputs and an
overriding clear (CLR) input. The parallel-in or
C
D
CLK INH
CLK
GND
4
5
6
7
8
13 QH
12 G
11 F
10 E
9 CLR
serial-in modes are established by the shift / load
(SH/LD) input. When high, SH/LD enables the serial (SER) data input and couples the eight flip-flops for serial
shifting with each clock (CLK) pulse. When low, the parallel (broadside) data inputs are enabled, and
synchronous loading occurs on the next clock pulse. During parallel loading, serial data flow is inhibited.
Clocking is accomplished on the low-to-high-level edge of CLK through a 2-input positive-NOR gate, permitting
one input to be used as a clock-enable or clock-inhibit function. Holding either CLK or CLK INH high inhibits
clocking; holding either low enables the other clock input. This allows the system clock to be free running, and
the register can be stopped on command with the other clock input. CLK INH should be changed to the high
level only when CLK is high. CLR overrides all other inputs, including CLK, and resets all flip-flops to zero.
ORDERING INFORMATION{
TA
PACKAGE‡
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
−40°C to 85°C
SOIC − D
TSSOP − PW
Tape and reel
Tape and reel
SN74HC166AIDRQ1
SN74HC166AIPWRQ1
HC166AI
HC166AI
For the most current package and ordering information, see the Package Option Addendum at the end of this
document, or see the TI web site at http://www.ti.com.
Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 2008, Texas Instruments Incorporated
1

SN74HC166A-Q1 Datasheet
SN74HC166AĆQ1
8ĆBIT PARALLELĆLOAD SHIFT REGISTER
SCLS538A − AUGUST 2003 − REVISED APRIL 2008
CLR
L
H
H
H
H
H
FUNCTION TABLE
INPUTS
SH/LD CLK INH CLK
X XX
X LL
L L
H L
H L
X H
SER
X
X
X
H
L
X
PARALLEL
A...H
X
X
a...h
X
X
X
OUTPUTS
INTERNAL
QA QB QH
L
QA0
a
H
L
QA0
L
QB0
b
QAn
QAn
QB0
L
QH0
h
QGn
QGn
QH0
logic diagram (positive logic)
15
SH/LD
ABCDE F G
2 3 4 5 10 11 12
1
SER
H
14
CLK INH
6
7
CLK
9
CLR
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
13
QH
2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265


Features Datasheet pdf SN74HC166AĆQ1 8ĆBIT PARALLELĆLOAD SHI FT REGISTER SCLS538A − AUGUST 2003 REVISED APRIL 2008 D Qualified for Automotive Applications D Low Input Cu rrent of 1 µA Max D ESD Protection Ex ceeds 2000 V Per D Synchronous Load M IL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) D Wide Operating Voltage Range of 2 V to 6 V D Direct Overriding Clear D Par allel-to-Serial Conversion D Outputs C an Drive Up To 10 LSTTL Loads D Low Pow er Consumption, 80-µA Max ICC D Typica l tpd = 13 ns D ±4-mA Output Drive at 5 V D OR PW PACKAGE (TOP VIEW) SER A B 1 2 3 16 VCC 15 SH/LD 14 H descrip tion/ordering information This parallel -in or serial-in, serial-out register f eatures gated clock (CLK, CLK INH) inpu ts and an overriding clear (CLR) input. The parallel-in or C D CLK INH CLK GN D 4 5 6 7 8 13 QH 12 G 11 F 10 E 9 CL R serial-in modes are established by t he shift / load (SH/LD) input. When hi gh, SH/LD enables the serial (SER) data input and couples the eight flip-.
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