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CD54HCT86 Dataheets PDF



Part Number CD54HCT86
Manufacturers Texas Instruments
Logo Texas Instruments
Description High-Speed CMOS Logic Quad 2-Input EXCLUSIVE-OR Gate
Datasheet CD54HCT86 DatasheetCD54HCT86 Datasheet (PDF)

Data sheet acquired from Harris Semiconductor SCHS137D August 1997 - Revised September 2003 CD54HC86, CD74HC86, CD54HCT86, CD74HCT86 High-Speed CMOS Logic Quad 2-Input EXCLUSIVE-OR Gate [ /Title (CD74 HC86, CD74 HCT86 ) /Subject (High Speed CMOS Logic Quad 2-Input EXCL USIVE OR Features Description • Typical Propagation Delay: CL = 15pF, TA = 25oC 9ns at VCC = 5V, • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . .

  CD54HCT86   CD54HCT86


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Data sheet acquired from Harris Semiconductor SCHS137D August 1997 - Revised September 2003 CD54HC86, CD74HC86, CD54HCT86, CD74HCT86 High-Speed CMOS Logic Quad 2-Input EXCLUSIVE-OR Gate [ /Title (CD74 HC86, CD74 HCT86 ) /Subject (High Speed CMOS Logic Quad 2-Input EXCL USIVE OR Features Description • Typical Propagation Delay: CL = 15pF, TA = 25oC 9ns at VCC = 5V, • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads • Wide Operating Temperature Range . . . -55oC to 125oC • Balanced Propagation Delay and Transition Times • Significant Power Reduction Compared to LSTTL Logic ICs • HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V • HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH Applications • Logical Comparators • Parity Generators and Checkers • Adders and Subtractors The ’HC86 and ’HCT86 contain four independent EXCLUSIVE OR gates in one package. They provide the system designer with a means for implementation of the EXCLUSIVE OR function. Logic gates utilize silicon gate CMOS technology to achieve operating speeds similar to LSTTL gates with the low power consumption of standard CMOS integrated circuits. All devices have the ability to drive 10 LSTTL loads. The HCT logic family is functionally pin compatible with the standard LS logic family. Ordering Information PART NUMBER CD54HC86F3A CD54HCT86F3A CD74HC86E CD74HC86M CD74HC86MT CD74HC86M96 CD74HCT86E CD74HCT86M CD74HCT86MT TEMP. RANGE (oC) PACKAGE -55 to 125 14 Ld CERDIP -55 to 125 14 Ld CERDIP -55 to 125 14 Ld PDIP -55 to 125 14 Ld SOIC -55 to 125 14 Ld SOIC -55 to 125 14 Ld SOIC -55 to 125 14 Ld PDIP -55 to 125 14 Ld SOIC -55 to 125 14 Ld SOIC CD74HCT86M96 -55 to 125 14 Ld SOIC NOTE: When ordering, use the entire part number. The suffix 96 denotes tape and reel. The suffix T denotes a small-quantity reel of 250. Pinout CD54HC86, CD54HCT86 (CERDIP) CD74HC86, CD74HCT86 (PDIP, SOIC) TOP VIEW 1A 1 1B 2 1Y 3 2A 4 2B 5 2Y 6 GND 7 14 VCC 13 4B 12 4A 11 4Y 10 3B 9 3A 8 3Y CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, Texas Instruments Incorporated 1 CD54HC86, CD74HC86, CD54HCT86, CD74HCT86 Functional Diagram 1 1A 2 1B 3 1Y 4 2A 5 2B 6 2Y 7 GND 14 VCC 13 4B 12 4A 11 4Y 10 3B 9 3A 8 3Y Logic Symbol TRUTH TABLE INPUTS nA nB LL LH HL HH H = High Voltage Level, L = Low Voltage Level OUTPUT nY L H H L nA nY nB 2 CD54HC86, CD74HC86, CD54HCT86, CD74HCT86 Absolute Maximum Ratings DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .±50mA Thermal Information Thermal Resistance (Typical, Note 1) θJA (oC/W) E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . 80 M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . 86 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. The package thermal impedance is calculated in accordance with JESD 51-7. DC Electrical Specifications PARAMETER HC TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads High Level Outp.


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