Document
Data sheet acquired from Harris Semiconductor SCHS143C
November 1997 - Revised August 2003
CD54HC125, CD74HC125, CD54HCT125, CD74HCT125
High-Speed CMOS Logic Quad Buffer, Three-State
[ /Title (CD74 HC125 , CD74 HCT12 5) /Subject (High Speed CMOS Logic Quad Buffer, ThreeState)
Features
Description
• Three-State Outputs
• Separate Output Enable Inputs
• Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL Logic ICs
• HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
• HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
The ’HC125 and ’HCT125 contain 4 independent three-state buffers, each having its own output enable input, which when “HIGH” puts the output in the high impedance state.
Ordering Information
PART NUMBER CD54HC125F3A CD54HCT125F3A CD74HC125E CD74HC125M CD74HC125MT CD74HC125M96 CD74HCT125E CD74HCT125M
TEMP. RANGE (oC)
PACKAGE
-55 to 125
14 Ld CERDIP
-55 to 125
14 Ld CERDIP
-55 to 125
14 Ld PDIP
-55 to 125
14 Ld SOIC
-55 to 125
14 Ld SOIC
-55 to 125
14 Ld SOIC
-55 to 125
14 Ld PDIP
-55 to 125
14 Ld SOIC
CD74HCT125MT
-55 to 125
14 Ld SOIC
CD74HCT125M96
-55 to 125
14 Ld SOIC
NOTE: When ordering, use the entire part number. The suffix 96 denotes tape and reel. The suffix T denotes a small-quantity reel of 250.
Pinout
CD54HC125, CD54HCT125 (CERDIP)
CD74HC125, CD74HCT125 (PDIP, SOIC) TOP VIEW
1OE 1 1A 2 1Y 3
2OE 4 2A 5 2Y 6
GND 7
14 VCC 13 4OE 12 4A 11 4Y 10 3OE 9 3A 8 3Y
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
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CD54HC125, CD74HC125, CD54HCT125, CD74HCT125
Functional Diagram
1 1OE
2 1A
4 2OE
5 2A
10 3OE
9 3A
13 4OE
12 4A
3 1Y
6 2Y
8 3Y
11 4Y
GND = 7 VCC = 14
TRUTH TABLE
INPUTS
nA nOE
HL
LL
XH
H= High Voltage Level L= Low Voltage Level X= Don’t Care Z= High Impedance, OFF State
OUTPUTS nY H L Z
Logic Diagram
nA nOE
P nY
n
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CD54HC125, CD74HC125, CD54HCT125, CD74HCT125
Absolute Maximum Ratings
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Drain Current, per Output, IO
For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . . ±35mA DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC . . . . ..