CD54HCT125

Data sheet acquired from Harris Semiconductor SCHS143C November 1997 - Revised August 2003 CD54HC125, CD74HC125, CD54HCT125, CD74HCT125 High-Speed CMOS Logic Quad Buffer, Three-State [ /Title (CD74 HC125 , CD74 HCT12 5) /Subject (High Speed CMOS Logic Quad Buffer, ThreeState) Features Description Three-State Outputs Separate Output Enable Inputs Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads Wide Operating Temperature Range . . . -55oC to 125oC Balanced Propagation Delay and Transition Times Significant Power Reduction Compared to LSTTL Logic ICs HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH The ’HC125 and ’HCT125 contain 4 independent three-state buffers, each having its own output enable input, which when “HIGH” puts the output in the high impedance state. Ordering Information PART NUMBER CD54HC125F3A CD54HCT125F3A CD74HC125E CD74HC125M CD74HC125MT CD74HC125M96 CD74HCT125E CD74HCT125M TEMP. RANGE (oC) PACKAGE -55 to 125 14 Ld CERDIP -55 to 125 14 Ld CERDIP -55 to 125 14 Ld PDIP -55 to 125 14 Ld SOIC -55 to 125 14 Ld SOIC -55 to 125 14 Ld SOIC -55 to 125 14 Ld PDIP -55 to 125 14 Ld SOIC CD74HCT125MT -55 to 125 14 Ld SOIC ...