Document
Data sheet acquired from Harris Semiconductor SCHS145E
August 1997 - Revised March 2004
CD54HC132, CD74HC132, CD54HCT132, CD74HCT132
High-Speed CMOS Logic Quad 2-Input NAND Schmitt Trigger
[ /Title (CD74 HC132 , CD74 HCT13 2) /Subject (High Speed CMOS Logic Quad 2-Input NAND Schmit
Features
Description
• Unlimited Input Rise and Fall Times
• Exceptionally High Noise Immunity
•
Typical Propagation Delay: CL = 15pF, TA = 25oC
10ns
at
VCC
=
5V,
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
The ’HC132 and ’HCT132 each contain four 2-input NAND Schmitt Triggers in one package. This logic device utilizes silicon gate CMOS technology to achieve operating speeds similar to LSTTL gates with the low power consumption of standard CMOS integrated circuits. All devices have the ability to drive 10 LSTTL loads. The HCT logic family is functionally pin compatible with the standard LS logic family.
Ordering Information
PART NUMBER
TEMP. RANGE (oC)
PACKAGE
• Significant Power Reduction Compared to LSTTL Logic ICs
• HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 37%, NIH = 51% of VCC at VCC = 5V
• HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
CD54HC132F3A CD54HCT132F3A CD74HC132E CD74HC132M CD74HC132MT CD74HC132M96 CD74HCT132E CD74HCT132M CD74HCT132MT
-55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125
14 Ld CERDIP 14 Ld CERDIP 14 Ld PDIP 14 Ld SOIC 14 Ld SOIC 14 Ld SOIC 14 Ld PDIP 14 Ld SOIC 14 Ld SOIC
CD74HCT132M96
-55 to 125
14 Ld SOIC
NOTE: When ordering, use the entire part number. The suffix 96 denotes tape and reel. The suffix T denotes a small-quantity reel of 250.
Pinout
CD54HC132, CD54HCT132 (CERDIP)
CD74HC132, CD74HCT132 (PDIP, SOIC) TOP VIEW
1A 1 1B 2 1Y 3 2A 4 2B 5 2Y 6 GND 7
14 VCC 13 4B 12 4A 11 4Y 10 3B 9 3A 8 3Y
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2004, Texas Instruments Incorporated
1
CD54HC132, CD74HC132, CD54HCT132, CD74HCT132 Functional Diagram
1 1A
2 1B
3 1Y
4 2A
5 2B
6 2Y
7 GND
14 VCC
13 4B
12 4A
11 4Y
10 3B
9 3A
8 3Y
Logic Symbol
TRUTH TABLE INPUTS nA nB LL LH HL HH H = High Voltage Level, L = Low Voltage Level
OUTPUT nY H H H L
nA nY
nB
2
CD54HC132, CD74HC132, CD54HCT132, CD74HCT132
Absolute Maximum Ratings
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Output Source o.