5490A

54/7490A 54LS/74LS90 DECADE COUNTER 90 CONNECTION DIAGRAM PINOUT A DESCRIPTION — The ’90 is a 4-stage ripple counter containing a high speed flip-flop acting as a divide-by-two and three flip-flops connected as a divideby-five counter. It can be connected to operate with a conventional BCD out­ put pattern or it can be connected to provide a 50% duty cycle output. In the BCD mode, HIGH signals on the Master Set (MS) inputs set the outputs to BCD nine. HIGH signals on the Master Reset (MR) inputs force all outputs LOW. For a similar counter with corner power pins, see the ’LS290; for dual versions, see the ’LS390 and ’LS490. ORDERING CODE: See Section 9 PKGS PIN OUT COMMERCIAL GRADE Vcc = +5.0 V ±5%, T a = 0°C to +70°C MILITARY GRADE Vcc = +5.0 V ±10%, TA = -55° C to +125° C Plastic DIP (P) A 7490APC, 74LS90PC Ceramic DIP (D) A 7490ADC, 74LS90DC 5490ADM, 54LS90DM Flatpak (F) A 7490AFC, 74LS90FC 5490AFM, 54LS90FM PKG TYPE 9A 6A 3I LOGIC SYMBOL 67 Vcc = Pin 5 GND = Pin 10 NC = Pins 4,13 INPUT LOADING/FAN-OUT: See Section 3 for U.L. defintions PIN NAMES DESCRIPTION CPo CPi MRi, MR2 MSi , MS2 Qo +2 Section Clock Input (Active Falling Edge) -H5 Section Clock Input (Active Falling Edge) Asynchronous Master Reset Inputs (Active HIGH) Asynchronous Master Set (Preset 9) Inputs (Active HIGH) -j-2 Section Output* -^-5 Section Outputs *The Qo output is guaranteed to drive the full rated fan-out plus the C P i input. 54/74 (U.L.) HIGH/LOW 2.0/2.0 3.0/3.0 1.0/1.0 1.0...