DUAL-PORT SRAM. 7133SA Datasheet

7133SA Datasheet PDF, Equivalent


Part Number

7133SA

Description

HIGH SPEED 2K x 16 DUAL-PORT SRAM

Manufacture

IDT

Total Page 17 Pages
PDF Download
Download 7133SA Datasheet


7133SA Datasheet
HIGH SPEED
2K X 16 DUAL-PORT
SRAM
7133SA/LA
7143SA/LA
Features
High-speed access
– Military: 35/55/70/90ns (max.)
– Industrial: 25ns (max.)
– Commercial: 20/25/35/45/55/70/90ns (max.)
Low-power operation
– IDT7133/43SA
Active: 1150mW (typ.)
Standby: 5mW (typ.)
– IDT7133/43LA
Active: 1050mW (typ.)
Standby: 1mW (typ.)
Versatile control for write: separate write control for lower
and upper byte of each port
Functional Block Diagram
R/WLUB
CEL
MASTER IDT7133 easily expands data bus width to 32 bits
or more using SLAVE IDT7143
On-chip port arbitration logic (IDT7133 only)
BUSY output flag on IDT7133; BUSY input on IDT7143
Fully asynchronous operation from either port
Battery backup operation–2V data retention
TTL-compatible; single 5V (±10%) power supply
Available in 68-pin ceramic PGA, Flatpack, PLCC and 100-
pin TQFP
Military product compliant to MIL-PRF-38535 QML
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Green parts available, see ordering information
R/WRUB
CER
R/WLLB
OEL
R/WRLB
OER
I/O8L - I/O15L
I/O0L - I/O7L
BUSYL(1)
A10L
A0L
I/O
CONTROL
I/O
CONTROL
ADDRESS
DECODER
11
CEL
MEMORY
ARRAY
ARBITRATION
LOGIC
(IDT7133 ONLY)
ADDRESS
DECODER
11
CER
NOTE:
1. IDT7133 (MASTER): BUSY is open drain output and requires pull-up resistor.
IDT7143 (SLAVE): BUSY is input.
I/O8R - I/O15R
I/O0R - I/O7R
BUSYR(1)
A10R
A0R
2746 drw 01
©2019 Integrated Device Technology, Inc.
1
AUGUST 2019
DSC 2746/16

7133SA Datasheet
7133SA/LA, 7143SA/LA
High-Speed 2K x 16 Dual-Port RAM
Description
The IDT7133/7143 are high-speed 2K x 16 Dual-Port Static RAMs.
The IDT7133 is designed to be used as a stand-alone 16-bit Dual-Port
RAM or as a “MASTER” Dual-Port RAM together with the IDT7143
“SLAVE” Dual-Port in 32-bit-or-more word width systems. Using the IDT
MASTER/SLAVE Dual-Port RAM approach in 32-bit-or-wider memory
system applications results in full-speed, error-free operation without the
need for additional discrete logic.
Both devices provide two independent ports with separate control,
Pin Configurations(1,2,3)
Military, Industrial and Commercial Temperature Ranges
address,andI/Opinsthatpermitindependent, asynchronousaccessfor
reads or writes to any location in memory. An automatic power down
feature,controlledby CE,permitstheon-chipcircuitryofeachporttoenter
a very low standby power mode.
Fabricated using CMOS high-performance technology. Low-power
(LA) versions offer battery backup data retention capability, with each port
typically consuming 200µW for a 2V battery.
The IDT7133/7143 devices have identical pinouts. Each is packed in
a 68-pin ceramic PGA, 68-pin flatpack, 68-pin PLCC and 100-pin TQFP.
Militarygradeproductismanufacturedincompliancewiththelatestrevision
of MIL-PRF-38535 QML, making it ideally suited to military temperature
applications demanding the highest level of performance and reliability.
I/O8R
I/O9R
I/O10R
I/O11R
I/O12R
I/O13R
I/O14R
I/O15R
GND(2)
R/WRUB
R/WRLB
OER
A10R
A9R
A8R
A7R
A6R
26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
27 9
28 8
29 7
30 6
31 5
32 4
33 3
34
7133/43
2
35
PLG68/FP68(4)
1
36 68
37
68-Pin PLCC/Flatpack
67
Top View
38 66
39 65
40 64
41 63
42 62
43 61
44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
I/O8L
I/O7L
I/O6L
I/O5L
I/O4L
I/O3L
I/O2L
I/O1L
I/O0L
VCC(1)
R/WLUB
R/WLLB
OEL
A10L
A9L
A8L
A7L
2746 drw 02
A6L
A7L
A8L
A9L
A10L
N/C
N/C
N/C
R/WLUB
CEL
N/C
R/WLLB
VCC
OEL
I/O0L
I/O1L
GND
NOTES:
I/O2L
I/O3L
1. Both VCC pins must be connected to the power supply to ensure reliable I/O4L
operation.
I/O5L
2.
Both GND pins must be connected to the ground supply to ensure reliable
operation.
I/O6L
I/O7L
I/O8L
3. J68-Package body is approximately 0.95 in x 0.95 in x 0.17 in.
I/O9L
F68-Package body is approximately 1.18 in x 1.18 in x 0.16 in.
PN100-Package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
76 50
77 49
78 48
79 47
80 46
81 45
82 44
83 43
84 42
85 41
86 40
87
7133/43
39
88
PNG100(4)
38
89
90
91
100-Pin TQFP
Top View
37
36
35
92 34
93 33
94 32
95 31
96 30
97 29
98 28
99 27
100 26
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
A5R
A6R
A7R
A8R
A9R
A10R
N/C
N/C
N/C
R/WRUB
CER
N/C
GND
R/WRLB
OER
I/O15R
GND
I/O14R
I/O13R
I/O12R
I/O11R
I/O10R
I/O9R
I/O8R
I/O7R
2746 drw 03
6.242


Features Datasheet pdf HIGH SPEED 2K X 16 DUAL-PORT SRAM 7133S A/LA 7143SA/LA Features ◆ High-speed access – Military: 35/55/70/90ns (ma x.) – Industrial: 25ns (max.) – Com mercial: 20/25/35/45/55/70/90ns (max.) ◆ Low-power operation – IDT7133/43S A Active: 1150mW (typ.) Standby: 5mW (t yp.) – IDT7133/43LA Active: 1050mW (t yp.) Standby: 1mW (typ.) ◆ Versatile control for write: separate write contr ol for lower and upper byte of each por t Functional Block Diagram R/WLUB CEL ◆ MASTER IDT7133 easily expands data bus width to 32 bits or more using SLAV E IDT7143 ◆ On-chip port arbitration logic (IDT7133 only) ◆ BUSY output fl ag on IDT7133; BUSY input on IDT7143 Fully asynchronous operation from eit her port ◆ Battery backup operation 2V data retention ◆ TTL-compatible; single 5V (±10%) power supply ◆ Avai lable in 68-pin ceramic PGA, Flatpack, PLCC and 100- pin TQFP ◆ Military pro duct compliant to MIL-PRF-38535 QML ◆ Industrial temperature range (–40°C to +85°C) is available for selected speeds ◆ Green parts availa.
Keywords 7133SA, datasheet, pdf, IDT, HIGH, SPEED, 2K, x, 16, DUAL-PORT, SRAM, 133SA, 33SA, 3SA, 7133S, 7133, 713, Equivalent, stock, pinout, distributor, price, schematic, inventory, databook, Electronic, Components, Parameters, parts, cross reference, chip, Semiconductor, circuit, Electric, manual, substitute




@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)