LMK03318 Generator Datasheet

LMK03318 Datasheet PDF, Equivalent


Part Number

LMK03318

Description

Ultra-Low-Noise Jitter Clock Generator

Manufacture

etcTI

Total Page 30 Pages
Datasheet
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LMK03318
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LMK03318
SNAS669E – SEPTEMBER 2015 – REVISED APRIL 2018
LMK03318 Ultra-Low-Noise Jitter Clock Generator Family With One PLL, Eight Outputs,
Integrated EEPROM
1 Features
1 Ultra-Low Noise, High Performance
– Jitter: 100-fs RMS Typical, FOUT > 100 MHz
– PSNR: –80 dBc, Robust Supply Noise
Immunity
• Flexible Device Options
– Up to 8 AC-LVPECL, AC-LVDS, AC-CML,
HCSL or LVCMOS Outputs, or Any
Combination
– Pin Mode, I2C Mode, EEPROM Mode
– 71-Pin Selectable Pre-programmed Default
Start-Up Options
• Dual Inputs With Automatic or Manual Selection
– Crystal Input: 10 to 52 MHz
– External Input: 1 to 300 MHz
• Frequency Margining Options
– Fine Frequency Margining Using Low-Cost
Pullable Crystal Reference
– Glitchless Coarse Frequency Margining (%)
Using Output Dividers
• Other Features
– Supply: 3.3-V Core, 1.8-V, 2.5-V, or 3.3-V
Output Supply
– Industrial Temperature Range (–40ºC to 85ºC)
SPACER
2 Applications
• Switches and Routers
• Network and Telecom Line Cards
• Servers and Storage Systems
• Wireless Base Station
• PCIe Gen1, Gen2, Gen3, Gen4
• Test and Measurement
• Broadcast Infrastructure
3 Description
The LMK03318 device is an ultra-low-noise
PLLATINUM™ clock generator with one fractional-N
frequency synthesizer with integrated VCO, flexible
clock distribution and fanout, and pin-selectable
configuration states stored in on-chip EEPROM. The
device can generate multiple clocks for various multi-
gigabit serial interfaces and digital devices, thus
reducing BOM cost and board area and improving
reliability by replacing multiple oscillators and clock
distribution devices. The ultra-low jitter reduces bit-
error rate (BER) in high-speed serial links.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
LMK03318
WQFN (48)
7.00 mm × 7.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
LMK03318 Simplified Block Diagram
PLL
2
Power
Conditioning
Output
Dividers
8
Output
Buffers
8
LMK03318
Ultra-high performance clock generator
Interface
I2C/ROM/
EEPROM
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

LMK03318
LMK03318
SNAS669E – SEPTEMBER 2015 – REVISED APRIL 2018
www.ti.com
Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 3
5 Description (continued)......................................... 4
6 Device Comparison Table..................................... 4
7 Pin Configuration and Functions ......................... 5
8 Specifications......................................................... 7
8.1 Absolute Maximum Ratings ...................................... 7
8.2 ESD Ratings.............................................................. 7
8.3 Recommended Operating Conditions....................... 8
8.4 Thermal Information .................................................. 8
8.5 Thermal Information .................................................. 8
8.6 Electrical Characteristics - Power Supply ................. 9
8.7 Pullable Crystal Characteristics (SECREF_P,
SECREF_N)............................................................. 10
8.8 Non-Pullable Crystal Characteristics (SECREF_P,
SECREF_N)............................................................. 11
8.9 Clock Input Characteristics (PRIREF_P/PRIREF_N,
SECREF_P/SECREF_N)......................................... 11
8.10 VCO Characteristics.............................................. 11
8.11 PLL Characteristics ............................................... 12
8.12 1.8-V LVCMOS Output Characteristics
(OUT[7:0]) ................................................................ 12
8.13 LVCMOS Output Characteristics (STATUS[1:0]).. 12
8.14 Open-Drain Output Characteristics
(STATUS[1:0]).......................................................... 13
8.15 AC-LVPECL Output Characteristics ..................... 13
8.16 AC-LVDS Output Characteristics.......................... 13
8.17 AC-CML Output Characteristics............................ 14
8.18 HCSL Output Characteristics................................ 14
8.19 Power-On Reset Characteristics........................... 14
8.20 2-Level Logic Input Characteristics
(HW_SW_CTRL, PDN, GPIO[5:0]).......................... 15
8.21 3-Level Logic Input Characteristics (REFSEL,
GPIO[3:1]) ................................................................ 15
8.22 Analog Input Characteristics (GPIO[5])................. 15
8.23 I2C-Compatible Interface Characteristics (SDA,
SCL) ......................................................................... 16
8.24 Typical 156.25-MHz Closed-Loop Output Phase
Noise Characteristics ............................................... 16
8.25 Typical 161.1328125-MHz Closed-Loop Output
Phase Noise Characteristics.................................... 17
8.26 Closed-Loop Output Jitter Characteristics ........... 17
8.27 PCIe Clock Output Jitter ....................................... 17
8.28 Typical Power Supply Noise Rejection
Characteristics ......................................................... 18
8.29 Typical Power-Supply Noise Rejection
Characteristics ......................................................... 18
8.30 Typical Closed-Loop Output Spur Characteristics 18
8.31 Typical Characteristics .......................................... 19
9 Parameter Measurement Information ................ 23
9.1 Test Configurations ................................................. 23
10 Detailed Description ........................................... 27
10.1 Overview ............................................................... 27
10.2 Functional Block Diagram ..................................... 27
10.3 Feature Description............................................... 28
10.4 Device Functional Modes...................................... 32
10.5 Programming......................................................... 50
10.6 Register Maps ....................................................... 71
11 Application and Implementation...................... 117
11.1 Application Information........................................ 117
11.2 Typical Applications ............................................ 117
12 Power Supply Recommendations ................... 127
12.1 Device Power Up Sequence ............................... 127
12.2 Device Power Up Timing .................................... 128
12.3 Power Down........................................................ 129
12.4 Power Rail Sequencing, Power Supply Ramp Rate,
and Mixing Supply Domains .................................. 129
12.5 Power Supply Bypassing .................................... 131
13 Layout................................................................. 133
13.1 Layout Guidelines ............................................... 133
13.2 Layout Example .................................................. 133
14 Device and Documentation Support ............... 135
14.1 Device Support.................................................... 135
14.2 Receiving Notification of Documentation
Updates.................................................................. 135
14.3 Community Resources........................................ 135
14.4 Trademarks ......................................................... 135
14.5 Electrostatic Discharge Caution .......................... 135
14.6 Glossary .............................................................. 135
15 Mechanical, Packaging, and Orderable
Information ......................................................... 135
2 Submit Documentation Feedback
Product Folder Links: LMK03318
Copyright © 2015–2018, Texas Instruments Incorporated


Features Product Folder Order Now Technical Doc uments Tools & Software Support & Com munity LMK03318 SNAS669E – SEPTEMBER 2015 – REVISED APRIL 2018 LMK03318 U ltra-Low-Noise Jitter Clock Generator F amily With One PLL, Eight Outputs, Inte grated EEPROM 1 Features •1 Ultra-Lo w Noise, High Performance – Jitter: 1 00-fs RMS Typical, FOUT > 100 MHz – P SNR: –80 dBc, Robust Supply Noise Imm unity • Flexible Device Options – U p to 8 AC-LVPECL, AC-LVDS, AC-CML, HCSL or LVCMOS Outputs, or Any Combination – Pin Mode, I2C Mode, EEPROM Mode – 71-Pin Selectable Pre-programmed Defau lt Start-Up Options • Dual Inputs Wit h Automatic or Manual Selection – Cry stal Input: 10 to 52 MHz – External I nput: 1 to 300 MHz • Frequency Margin ing Options – Fine Frequency Marginin g Using Low-Cost Pullable Crystal Refer ence – Glitchless Coarse Frequency Ma rgining (%) Using Output Dividers • O ther Features – Supply: 3.3-V Core, 1 .8-V, 2.5-V, or 3.3-V Output Supply – Industrial Temperature Range (–40ºC to 85ºC) SPACER 2 Applic.
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