LMK03000 Conditioner Datasheet

LMK03000 Datasheet PDF, Equivalent


Part Number

LMK03000

Description

Clock Conditioner

Manufacture

etcTI

Total Page 30 Pages
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Download LMK03000 Datasheet PDF


LMK03000
LMK03000, LMK03000C, LMK03000D, LMK03001
LMK03001C, LMK03001D, LMK03033, LMK03033C
www.ti.com
SNAS381O – NOVEMBER 2006 – REVISED MARCH 2013
LMK03000 Family Precision Clock Conditioner with Integrated VCO
Check for Samples: LMK03000, LMK03000C, LMK03000D, LMK03001, LMK03001C, LMK03001D, LMK03033, LMK03033C
1 FEATURES
12
• Integrated VCO with Very Low Phase Noise
Floor
• Integrated Integer-N PLL with Outstanding
Normalized Phase Noise Contribution of -224
dBc/Hz
• VCO Divider Values of 2 to 8 (All Divides)
• Channel Divider Values of 1, 2 to 510 (even
divides)
• LVDS and LVPECL Clock Outputs
• Partially Integrated Loop Filter
• Dedicated Divider and Delay Blocks on Each
Clock Output
• Pin Compatible Family of Clocking Devices
• 3.15 to 3.45 V Operation
• Package: 48 Pin WQFN (7.0 x 7.0 x 0.8 mm)
• 200 fs RMS Clock Generator Performance (10
Hz to 20 MHz) with a Clean Input Clock
1.1 TARGET APPLICATIONS
• Data Converter Clocking
• Networking, SONET/SDH, DSLAM
• Wireless Infrastructure
• Medical
• Test and Measurement
• Military / Aerospace
Device
LMK03000C
LMK03000
LMK03000D
LMK03001C
LMK03001
LMK03001D
LMK03033C
LMK03033
Outputs
3 LVDS
5 LVPECL
4 LVDS
4 LVPECL
VCO
Tuning Range RMS Jitter
(MHz)
(fs)
400
1185 - 1296
800
1200
400
1470 - 1570
800
1200
1843 - 2160
500
800
Recovered
³GLUW\´ FORFN RU
clean clock
OSCin
CLKout0
LMK0300xx CLKout1
Precision Clock
Conditioner
CLKout4
CLKout7
Fout
LMX2531
PLL+VCO
Serializer/
Deserializer
FPGA
> 1 Gsps
ADC
DAC
0XOWLSOH ³FOHDQ´ FORFNV DW
different frequencies
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date. Products conform to
specifications per the terms of the Texas Instruments standard warranty. Production
processing does not necessarily include testing of all parameters.
Copyright © 2006–2013, Texas Instruments Incorporated

LMK03000
LMK03000, LMK03000C, LMK03000D, LMK03001
LMK03001C, LMK03001D, LMK03033, LMK03033C
SNAS381O – NOVEMBER 2006 – REVISED MARCH 2013
www.ti.com
1.2 DESCRIPTION
The LMK03000 family of precision clock conditioners combine the functions of jitter
cleaning/reconditioning, multiplication, and distribution of a reference clock. The devices integrate a
Voltage Controlled Oscillator (VCO), a high performance Integer-N Phase Locked Loop (PLL), a partially
integrated loop filter, and up to eight outputs in various LVDS and LVPECL combinations.
The VCO output is optionally accessible on the Fout port. Internally, the VCO output goes through a VCO
Divider to feed the various clock distribution blocks.
Each clock distribution block includes a programmable divider, a phase synchronization circuit, a
programmable delay, a clock output mux, and an LVDS or LVPECL output buffer. This allows multiple
integer-related and phase-adjusted copies of the reference to be distributed to eight system components.
The clock conditioners come in a 48-pin WQFN package and are footprint compatible with other clocking
devices in the same family.
1 FEATURES ............................................... 1
1.1 TARGET APPLICATIONS ........................... 1
1.2 DESCRIPTION ...................................... 2
2 Device Information ...................................... 3
2.1 Functional Block Diagram ........................... 3
2.2 Connection Diagram ................................. 4
3 Electrical Specifications ............................... 6
3.1 Absolute Maximum Ratings .......................... 6
3.2 Recommended Operating Conditions ............... 6
3.3 Package Thermal Resistance ....................... 6
3.4 Electrical Characteristics ............................ 7
3.5 Serial Data Timing Diagram ........................ 11
4 Measurement Definitions ............................ 12
4.1 Charge Pump Current Specification Definitions .... 12
5 Typical Performance Characteristics ............. 13
6 Functional Description ............................... 15
6.1 BIAS PIN ........................................... 15
6.2 LDO BYPASS ...................................... 15
6.3 OSCILLATOR INPUT PORT (OSCin, OSCin*) .... 15
6.4 LOW NOISE, FULLY INTEGRATED VCO ......... 15
6.5 CLKout DELAYS ................................... 15
6.6 LVDS/LVPECL OUTPUTS ......................... 16
6.7 GLOBAL CLOCK OUTPUT SYNCHRONIZATION 16
6.8 CLKout OUTPUT STATES ......................... 17
6.9 GLOBAL OUTPUT ENABLE AND LOCK DETECT 17
6.10 POWER ON RESET ............................... 17
6.11 DIGITAL LOCK DETECT ........................... 18
7 General Programming Information ................ 19
7.1 RECOMMENDED PROGRAMMING SEQUENCE . 19
7.2 REGISTER R0 to R7 ............................... 22
7.3 REGISTER R8 ..................................... 24
7.4 REGISTER R9 ...................................... 24
7.5 REGISTER R11 .................................... 24
7.6 REGISTER R13 .................................... 24
7.7 REGISTER R14 .................................... 25
7.8 REGISTER R15 .................................... 27
8 Application Information .............................. 28
8.1 SYSTEM LEVEL DIAGRAM ........................ 28
8.2 BIAS PIN ........................................... 28
8.3 LDO BYPASS ...................................... 28
8.4 LOOP FILTER ...................................... 29
8.5 CURRENT CONSUMPTION / POWER
DISSIPATION CALCULATIONS ................... 30
8.6 THERMAL MANAGEMENT ........................ 31
8.7 TERMINATION AND USE OF CLOCK OUTPUTS
(DRIVERS) ......................................... 32
8.8 OSCin INPUT ...................................... 36
8.9 MORE THAN EIGHT OUTPUTS WITH AN
LMK03000 FAMILY DEVICE ....................... 37
Revision History ............................................ 38
2 Contents
Copyright © 2006–2013, Texas Instruments Incorporated
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Product Folder Links: LMK03000 LMK03000C LMK03000D LMK03001 LMK03001C LMK03001D LMK03033
LMK03033C


Features LMK03000, LMK03000C, LMK03000D, LMK03001 LMK03001C, LMK03001D, LMK03033, LMK030 33C www.ti.com SNAS381O – NOVEMBER 2006 – REVISED MARCH 2013 LMK03000 F amily Precision Clock Conditioner with Integrated VCO Check for Samples: LMK0 3000, LMK03000C, LMK03000D, LMK03001, L MK03001C, LMK03001D, LMK03033, LMK03033 C 1 FEATURES 12 • Integrated VCO wit h Very Low Phase Noise Floor • Integr ated Integer-N PLL with Outstanding Nor malized Phase Noise Contribution of -22 4 dBc/Hz • VCO Divider Values of 2 to 8 (All Divides) • Channel Divider Va lues of 1, 2 to 510 (even divides) • LVDS and LVPECL Clock Outputs • Part ially Integrated Loop Filter • Dedica ted Divider and Delay Blocks on Each Cl ock Output • Pin Compatible Family of Clocking Devices • 3.15 to 3.45 V Op eration • Package: 48 Pin WQFN (7.0 x 7.0 x 0.8 mm) • 200 fs RMS Clock Gen erator Performance (10 Hz to 20 MHz) wi th a Clean Input Clock 1.1 TARGET APPL ICATIONS • Data Converter Clocking • Networking, SONET/SDH, DSLAM • Wireless Infrastructu.
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