LMK03002 Conditioner Datasheet

LMK03002 Datasheet PDF, Equivalent


Part Number

LMK03002

Description

Clock Conditioner

Manufacture

etcTI

Total Page 30 Pages
PDF Download
Download LMK03002 Datasheet PDF


LMK03002
LMK03002
www.ti.com
SNAS414E – AUGUST 2007 – REVISED APRIL 2013
LMK03002 /LMK03002C Precision Clock Conditioner with Integrated VCO
Check for Samples: LMK03002
FEATURES
1
2 Integrated VCO with Very Low Phase Noise
Floor
• Integrated Integer-N PLL with Outstanding
Normalized Phase Noise Contribution of
-224 dBc/Hz
• Clock Generator Performance (10 Hz - 20 MHz)
– LMK03002C: 200 fs RMS Jitter
• Jitter Cleaner Performance Grade (12 kHz to
20 MHz)
– LMK03002: 800 fs RMS Jitter
– LMK03002C: 400 fs RMS Jitter
• VCO Frequency: 1566 to 1724 MHz
• Clock Output Frequency Range of 1 to 862
MHz
• 4 LVPECL Clock Outputs
• Partially Integrated Loop Filter
• Dedicated Divider and Delay Blocks on Each
Clock Output
• Pin Compatible Family of Clocking Devices
• 3.15 to 3.45 V Operation
• Package: 48 Pin WQFN (7.0 x 7.0 x 0.8 mm)
TARGET APPLICATIONS
• Data Converter Clocking
• Networking, SONET/SDH, DSLAM
• Wireless Infrastructure
• Medical
• Test and Measurement
• Military / Aerospace
DESCRIPTION
The LMK03002/LMK03002C precision clock
conditioners combine the functions of jitter
cleaning/reconditioning, multiplication, and distribution
of a reference clock. The devices integrate a Voltage
Controlled Oscillator (VCO), a high performance
Integer-N Phase Locked Loop (PLL), a partially
integrated loop filter, and four LVPECL clock output
distribution blocks.
The VCO output is optionally accessible on the Fout
port. Internally, the VCO output goes through a VCO
Divider to feed the various clock distribution blocks.
Each clock distribution block includes a
programmable divider, a phase synchronization
circuit, a programmable delay, a clock output mux,
and an LVPECL output buffer. This allows multiple
integer-related and phase-adjusted copies of the
reference to be distributed to four system
components.
The clock conditioners come in a 48-pin WQFN
package and are footprint compatible with other
clocking devices in the same family.
Recovered
³GLUW\´ FORFN RU
clean clock
OSCin
CLKout0
LMK0300xx CLKout1
Precision Clock
Conditioner
Fout
CLKout2
CLKout3
LMX2531
PLL+VCO
Serializer/
Deserializer
FPGA
> 1 Gsps
ADC
DAC
0XOWLSOH ³FOHDQ´ FORFNV DW
different frequencies
Figure 1. System Diagram
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2013, Texas Instruments Incorporated

LMK03002
LMK03002
SNAS414E – AUGUST 2007 – REVISED APRIL 2013
Functional Block Diagram
OSCin
OSCin*
R Divider
N Divider
CLK
DATA
LE
PWire
Port
Control
Registers
Phase
Detector
Partially
Integrated
Loop Filter
Internal
VCO
Distribution
Path
Divider
VCO
Divider
Delay
Mux
Divider
Delay
Mux
GOE
SYNC*
Device
Control
LD
Clock Buffers
Divider
Delay
Mux
Divider
Delay
Mux
www.ti.com
Fout
CLKout0
CLKout0*
CLKout1
CLKout1*
CLKout2
CLKout2*
CLKout3
CLKout3*
2 Submit Documentation Feedback
Product Folder Links: LMK03002
Copyright © 2007–2013, Texas Instruments Incorporated


Features LMK03002 www.ti.com SNAS414E – AUGUS T 2007 – REVISED APRIL 2013 LMK03002 /LMK03002C Precision Clock Conditioner with Integrated VCO Check for Samples: LMK03002 FEATURES 1 •2 Integrated V CO with Very Low Phase Noise Floor • Integrated Integer-N PLL with Outstandi ng Normalized Phase Noise Contribution of -224 dBc/Hz • Clock Generator Perf ormance (10 Hz - 20 MHz) – LMK03002C: 200 fs RMS Jitter • Jitter Cleaner P erformance Grade (12 kHz to 20 MHz) – LMK03002: 800 fs RMS Jitter – LMK030 02C: 400 fs RMS Jitter • VCO Frequenc y: 1566 to 1724 MHz • Clock Output Fr equency Range of 1 to 862 MHz • 4 LVP ECL Clock Outputs • Partially Integra ted Loop Filter • Dedicated Divider a nd Delay Blocks on Each Clock Output Pin Compatible Family of Clocking Dev ices • 3.15 to 3.45 V Operation • P ackage: 48 Pin WQFN (7.0 x 7.0 x 0.8 mm ) TARGET APPLICATIONS • Data Convert er Clocking • Networking, SONET/SDH, DSLAM • Wireless Infrastructure • Medical • Test and Measurement • Military / Aerospace DESCRIPTION T.
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