C8051F544 MCU Datasheet

C8051F544 Datasheet PDF, Equivalent


Part Number

C8051F544

Description

Mixed Signal ISP Flash MCU

Manufacture

Silicon Laboratories

Total Page 30 Pages
PDF Download
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C8051F544
Analog Peripherals
- 12-Bit ADC
Up to 200 ksps
Up to 25 external single-ended inputs
VREF from on-chip VREF, external pin or VDD
Internal or external start of conversion source
Built-in temperature sensor
- Two Comparators
Programmable hysteresis and response time
Configurable as interrupt or reset source
Low current
On-Chip Debug
- On-chip debug circuitry facilitates full speed, non-
intrusive in-system debug (no emulator required)
- Provides breakpoints, single stepping,
inspect/modify memory and registers
- Superior performance to emulation systems using
ICE-chips, target pods, and sockets
- Low cost, complete development kit
Supply Voltage 1.8 to 5.25 V
- Typical operating current: 19 mA at 50 MHz;
Typical stop mode current: 1 µA
High-Speed 8051 µC Core
- Pipelined instruction architecture; executes 70% of
instructions in 1 or 2 system clocks
- Up to 50 MIPS throughput with 50 MHz clock
- Expanded interrupt handler
C8051F54x
Mixed Signal ISP Flash MCU Family
Memory
- 1280 bytes internal data RAM (256 + 1024 XRAM)
- 16 or 8 kB Flash; In-system programmable in
512-byte Sectors
Digital Peripherals
- 25 or 18 Port I/O; All 5 V tolerant
- LIN 2.1 Controller (Master and Slave capable); no
crystal required
- Hardware enhanced UART, SMBus™, and
enhanced SPI™ serial ports
- Four general purpose 16-bit counter/timers
- 16-Bit programmable counter array (PCA) with six
capture/compare modules and enhanced PWM
functionality
Clock Sources
- Internal 24 MHz with ±0.5% accuracy master LIN
operation
- External oscillator: Crystal, RC, C, or clock
(1 or 2 pin modes)
- Can switch between clock sources on-the-fly;
useful in power saving modes
Packages
- 32-Pin QFP/QFN (C8051F540/1/4/5)
- 24-Pin QFN (C8051F542/3/6/7)
Automotive Qualified
- Temperature Range: –40 to +125 °C
- Compliant to AEC-Q100
ANALOG
PERIPHERALS
A 12-bit
M
U
200 ksps
TEMP
SENSOR
X ADC
Voltage VREG
Comparators 0-1 VREF
DIGITAL I/O
UART 0
SMBus
SPI
PCA
Timers 0-3
LIN
Ports 0-3
Crossbar
24 MHz PRECISION
INTERNAL OSCILLATOR
2x Clock Multiplier
HIGH-SPEED CONTROLLER CORE
16 kB
ISP FLASH
FLEXIBLE
INTERRUPTS
8051 CPU
(50 MIPS)
DEBUG
CIRCUITRY
1 kB XRAM
POR WDT
Rev. 1.1 4/11
Copyright © 2011 by Silicon Laboratories
C8051F540/1/2/3/4/5/6/7

C8051F544
C8051F54x
2 Rev. 1.1


Features Analog Peripherals - 12-Bit ADC • Up t o 200 ksps • Up to 25 external single -ended inputs • VREF from on-chip VRE F, external pin or VDD • Internal or external start of conversion source • Built-in temperature sensor - Two Comp arators • Programmable hysteresis and response time • Configurable as inte rrupt or reset source • Low current O n-Chip Debug - On-chip debug circuitry facilitates full speed, non- intrusive in-system debug (no emulator required) - Provides breakpoints, single stepping , inspect/modify memory and registers - Superior performance to emulation syst ems using ICE-chips, target pods, and s ockets - Low cost, complete development kit Supply Voltage 1.8 to 5.25 V - Typ ical operating current: 19 mA at 50 MHz ; Typical stop mode current: 1 µA High -Speed 8051 µC Core - Pipelined instru ction architecture; executes 70% of ins tructions in 1 or 2 system clocks - Up to 50 MIPS throughput with 50 MHz clock - Expanded interrupt handler C8051F54x Mixed Signal ISP Flash MCU Family Memory.
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