HC55130 UniSLIC14 Datasheet

HC55130 Datasheet PDF, Equivalent


Part Number

HC55130

Description

Low Power UniSLIC14

Manufacture

Intersil

Total Page 30 Pages
PDF Download
Download HC55130 Datasheet PDF


HC55130
HC55120, HC55121, HC55130, HC55131, HC55140,
® HC55141, HC55142, HC55143, HC55150, HC55151
Data Sheet
July 2004
FN4659.11
Low Power UniSLIC14 Family
Features
The UniSLIC14 is a family of Ultra Low Power SLICs. The
feature set and common pinouts of the UniSLIC14 family
positions it as a universal solution for: Plain Old Telephone
Service (POTS), PBX, Central Office, Loop Carrier, Fiber in
the Loop, ISDN-TA and NT1+, Pairgain and Wireless Local
Loop.
The UniSLIC14 family achieves its ultra low power operation
through: Its automatic single and dual battery selection (based
on line length) and battery tracking anti clipping to ensure the
maximum loop coverage on the lowest battery voltage. This
architecture is ideal for power critical applications such as
ISDN NT1+, Pairgain and Wireless local loop products.
• Ultra Low Active Power (OHT) < 60mW
• Single/Dual Battery Operation
• Automatic Silent Battery Selection
• Power Management/Shutdown
• Battery Tracking Anti Clipping
• Single 5V Supply with 3V Compatible Logic
• Zero Crossing Ring Control
- Zero Voltage On/Zero Current Off
• Tip/Ring Disconnect
• Pulse Metering Capability
• 4 Wire Loopback
The UniSLIC14 family has many user programmable features.
This family of SLICs delivers a low noise, low component
count solution for Central Office and Loop Carrier universal
voice grade designs. The product family integrates advanced
pulse metering, test and signaling capabilities, and zero
crossing ring control.
The UniSLIC14 family is designed in the Intersil “Latch” free
Bonded Wafer process. This process dielectrically isolates the
active circuitry to eliminate any leakage paths as found in our
competition’s JI process. This makes the UniSLIC14 family
compliant with “hot plug” requirements and operation in harsh
outdoor environments.
Block Diagram
RRLY
TRLY1
TRLY2
DT
DR
RING AND TEST
RELAY DRIVERS
ZERO CURRENT
CROSSING
RING TRIP
DETECTOR
POLARITY
REVERSAL
TIP
RING
BGND
AGND
2-WIRE
INTERFACE
VBH
VBL
VCC
BATTERY
SELECTION
AND
BIAS
NETWORK
STATE
DECODER
AND
DETECTOR
LOGIC
LOOP CURRENT
DETECTOR
GKD/LOOP LENGTH
DETECTOR
C1
C2
C3
C4
C5
SHD
GKD_LVM
CRT_REV_LVM
LINE FEED
CONTROL
4-WIRE INTERFACE
VF SIGNAL PATH
PULSE METERING
SIGNAL PATH
ILIM
RSYNC_REV
ROH
CDC
RDC_RAC
RD
VTX
VRX
PTG
ZT
CH
• Programmable Current Feed
• Programmable Resistive Feed
• Programmable Loop Detect Threshold
• Programmable On-Hook and Off-Hook Overheads
• Programmable Overhead for Pulse Metering
• Programmable Polarity Reversal Time
• Selectable Transmit Gain 0dB/-6dB
• 2 Wire Impedance Set by Single Network
• Loop and Ground Key Detectors
• On-Hook Transmission
• Common Pinout
• Pb-free Available
• HC55121
- Polarity Reversal
• HC55130
- -63dB Longitudinal Balance
• HC55140
- Polarity Reversal
- Ground Start
- Line Voltage Measurement
- 2 Wire Loopback
- -63dB Longitudinal Balance
• HC55142
- Polarity Reversal
- Ground Start
- Line Voltage Measurement
- 2.2VRMS Pulse Metering
- 2 Wire Loopback
• HC55150
- Polarity Reversal
- Line Voltage Measurement
- 2.2VRMS Pulse Metering
- 2 Wire Loopback
Related Literature
• AN9871, User’s Guide for UniSLIC14 Eval Board
SPM • AN9903, UniSLIC14 and TI TCM38C17
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2001, 2002, 2004. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.

HC55130
HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151
Ordering Information
PART
NUMBER
MAX
LOOP
CURRENT POLARITY
(mA) REVERSAL
GND
START
LINE
VOLTAGE
GND
KEY
MEASUREMENT
PULSE
METERING
2 TEST
RELAY
DRIVERS
2 WIRE
LOOP-
BACK
TEMP
LONGITUDINAL RANGE
BALANCE
(°C)
PKG.
DWG. #
HC55120CB
30
53dB
0 to 70 M28.3
SOIC
HC55120CBZ
Pb-free (Note)
30
53dB
0 to 70 M28.3
SOIC
HC55120CM
30
53dB
0 to 70 N28.45
PLCC
HC55121IB
30
53dB
-40 to M28.3
85 SOIC
HC55121IBZ
Pb-free (Note)
30
53dB
-40 to M28.3
85 SOIC
HC55121IM
30
53dB
-40 to N28.45
85 PLCC
HC55130IB
45
63dB
-40 to M28.3
85 SOIC
HC55130IBZ
Pb-free (Note)
45
63dB
-40 to M28.3
85 SOIC
HC55130IBZ96
Pb-free (Note)
45
63dB
-40 to M28.3
85 SOIC
HC55130IM
45
63dB
-40 to N28.45
85 PLCC
HC55131IM
45
63dB
-40 to N32.45x55
85 PLCC
HC55140IB
45 • • • •
63dB
-40 to M28.3
85 SOIC
HC55140IBZ
Pb-free (Note)
45 • • • •
63dB
-40 to M28.3
85 SOIC
HC55140IM
45 • • • •
63dB
-40 to N28.45
85 PLCC
HC55141IM
45 • • • •
63dB
-40 to N32.45x55
85 PLCC
HC55142IB
45 • • • •
63dB
-40 to M28.3
85 SOIC
HC55142IBZ
Pb-free (Note)
45 • • • •
63dB
-40 to M28.3
85 SOIC
HC55142IM
45 • • • •
63dB
-40 to N28.45
85 PLCC
HC55143IM
45 • • • •
••
63dB
-40 to N32.45x55
85 PLCC
HC55150CB
45
••
55dB
0 to 70 M28.3
SOIC
HC55150CBZ
Pb-free (Note)
45
••
55dB
0 to 70 M28.3
SOIC
HC55150CM
45
••
55dB
0 to 70 N28.45
PLCC
HC55151CM
45
••
55dB
0 to 70 N32.45x55
PLCC
HC5514XEVAL1
Evaluation board
Available by placing SLIC in Test mode.
NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak
reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J Std-020B.
2


Features HC55120, HC55121, HC55130, HC55131, HC55 140, ® HC55141, HC55142, HC55143, HC55 150, HC55151 Data Sheet July 2004 FN 4659.11 Low Power UniSLIC14 Family Fe atures The UniSLIC14 is a family of Ul tra Low Power SLICs. The feature set an d common pinouts of the UniSLIC14 famil y positions it as a universal solution for: Plain Old Telephone Service (POTS) , PBX, Central Office, Loop Carrier, Fi ber in the Loop, ISDN-TA and NT1+, Pair gain and Wireless Local Loop. The UniSL IC14 family achieves its ultra low powe r operation through: Its automatic sing le and dual battery selection (based on line length) and battery tracking anti clipping to ensure the maximum loop co verage on the lowest battery voltage. T his architecture is ideal for power cri tical applications such as ISDN NT1+, P airgain and Wireless local loop product s. • Ultra Low Active Power (OHT) < 60mW • Single/Dual Battery Operation • Automatic Silent Battery Selection • Power Management/Shutdown • Battery Tracking Anti Clipping • Single .
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