Audio Decoder. CS49311 Datasheet

CS49311 Decoder. Datasheet pdf. Equivalent

CS49311 Datasheet
Recommendation CS49311 Datasheet
Part CS49311
Description Multi-Standard Audio Decoder
Feature CS49311; CS49300 Family DSP Multi-Standard Audio Decoder Family Features Description z CS4930X: DVD Audio.
Manufacture Cirrus Logic
Datasheet
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Cirrus Logic CS49311
CS49300 Family DSP
Multi-Standard Audio Decoder Family
Features
Description
z CS4930X: DVD Audio Sub-family
— PES Layer decode for A/V sync
— DVD Audio Pack Layer Support
— Meridian Lossless Packing Specification (MLP)™
— Dolby Digital™, Dolby Pro Logic II™
— MPEG-2, Advanced Audio Coding Algorithm (AAC)
— MPEG Multichannel
— DTS Digital Surround™, DTS-ES Extended Surround™
z CS4931X: Broadcast Sub-family
— PES Layer decode for A/V sync
— Dolby Digital
— MPEG-2, Advanced Audio Coding Algorithm (AAC)
— MPEG-1 (Layers 1, 2, 3) Stereo
— MPEG-2 (Layers 2, 3) Stereo
z CS4932X: AVR Sub-family
— Dolby Digital, Dolby Pro Logic II
— DTS & DTS-ES decoding with integrated DTS tables
— Cirrus Original Surround 5.1 PCM Enhancement
— MPEG-2, Advanced Audio Coding Algorithm (AAC)
— MPEG Multichannel
— MP3 (MPEG-1, Layer 3)
z CS49330: General Purpose Audio DSP
— THX® Surround EX™ and THX® Ultra2 Cinema
— General Purpose AVR and Broadcast Audio Decoder
(MPEG Multichannel, MPEG Stereo, MP3, C.O.S.)
— Car Audio
z Features are a super-set of the CS4923/4/5/6/7/8/9
— 8 channel output, including dual zone output capability
— Dynamic Channel Remapability
— Supports up to 192 kHz Fs @ 24-bit throughput
— Increased memory/MIPs
— SRAM Interface for increased delay and buffer capability
— Dual-Precision Bass Manager
— Enhance your system functionality via firmware
upgrades through the Crystal WareTM Software
Licensing Program
The CS493XX is a family of multichannel audio decoders
intended to supersede the CS4923/4/5/6/7/8/9 family as the
leader of audio decoding in both the DVD, broadcast and
receiver markets. The family will be split into parts tailored for
each of these distinct market segments.
For the DVD market, parts will be offered which support Meridian
Lossless Packing (MLP), Dolby Digital, Dolby Pro Logic II,
MPEG Multichannel, DTS Digital Surround, DTS-ES, AAC, and
subsets thereof. For the receiver market, parts will be offered
which support Dolby Digital, Dolby Pro Logic II, MPEG
Multichannel, DTS Digital Surround, DTS-ES, AAC, and various
virtualizers and PCM enhancement algorithms such as HDCD®,
DTS Neo:6TM, LOGIC7®, and SRS Circle Surround II®. For the
broadcast market, parts will be offered which support Dolby
Digital, AAC, MPEG-1, Layers 1,2 and 3, MPEG-2, Layers 2 and
3.
Under the Crystal brand, Cirrus Logic is the only single supplier
of high-performance 24-bit multi-standard audio DSP decoders,
DSP firmware, and high-resolution data converters. This
combination of DSPs, system firmware, and data converters
simplify rapid creation of world-class high-fidelity digital audio
products for the Internet age.
Ordering Information: See page 87
CS49300
CS49310
CS49311
CS49312
CS49325
CS49326
CS49329
CS49330
CS49330
CS49330
APPLICATION
DVD Audio
Broadcast
Broadcast
Broadcast
AVR
AVR
AVR
Car Audio DSP
General Purpose
Post-Processor
CORE DECODER FUNCTIONALITY
MLP, AC-3, AAC, DTS, MPEG 5.1, MP3, etc.
AAC, AC-3, MPEG Stereo, MP3, etc.
AAC, MPEG Stereo, MP3, etc.
AC-3, MPEG Stereo, MP3, etc.
AC-3, COS, MPEG 5.1, MP3, etc.
AC-3, DTS, COS, MPEG 5.1, MP3, etc.
AC-3, AAC, DTS, MPEG 5.1, MP3, etc.
Car Audio Code
MPEG 5.1, MPEG Stereo, MP3, C.O.S., etc
DPP, THX Surround EX, THX Ultra2 Cinema
RESET
RD, WR, SCDIO,
DATA7:0,
R/W, DS, SCDOUT,
EMAD7:0,
EMOE, EMWR, PSEL, A0, A1,
GPIO7:0 CS GPIO11 GPIO10 GPIO9 SCCLK SCDIN
ABOOT,
INTREQ
EXTMEM,
GPIO8
CMPDAT,
SDATAN2
CMPCLK,
SCLKN2
CMPREQ,
LRCLKN2
SCLKN1,
STCCLK2
LRCLKN1
SDATAN1
CLKIN
CLKSEL
Compressed
Data Input
Interface
Framer
Shifter
Digital
Audio
Input
Interface
Input
Buffer
Controller
RAM Input
Buffer
PLL
Clock Manager
Parallel or Serial Host Interface
24-Bit
DSP Processing
RAM RAM
Program Data
Memory Memory
ROM ROM
Program Data
Memory Memory
STC
RAM
Output
Buffer
DD
DC
Output
Formatter
MCLK
SCLK
LRCLK
AUDATA[2.0]
XMT958/AUDATA3
FILT2 FILT1 VA AGND
DGND[3:1] VD[3:1]
http://www.cirrus.com
Copyright © Cirrus Logic, Inc. 2006
(All Rights Reserved)
APR ‘06
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Cirrus Logic CS49311
CS49300 Family DSP
TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS ................................................................. 7
1.1 Specified Operating Conditions .................................................................................. 7
1.2 Absolute Maximum Ratings ........................................................................................ 7
1.3 Thermal Data .............................................................................................................. 7
1.4 Digital D.C. Characteristics ......................................................................................... 8
1.5 Power Supply Characteristics ..................................................................................... 8
1.6 Switching Characteristics — RESET ........................................................................ 9
1.7 Switching Characteristics — CLKIN ............................................................................ 9
1.8 Switching Characteristics — Intel® Host Mode ......................................................... 10
1.9 Switching Characteristics — Motorola® Host Mode .................................................. 12
1.10 Switching Characteristics — SPI™ Control Port ..................................................... 14
1.11 Switching Characteristics — I2C® Control Port ....................................................... 16
1.12 Switching Characteristics — Digital Audio Input ..................................................... 18
1.13 Switching Characteristics — Serial Bursty Data Input ............................................. 20
1.14 Switching Characteristics — Parallel Data Input ..................................................... 21
1.15 Switching Characteristics — Digital Audio Output ................................................... 22
2. FAMILY OVERVIEW ....................................................................................................... 24
2.1 CS493XX Document Strategy .................................................................................. 24
2.2 Multichannel Decoder Family of Parts ...................................................................... 24
3. TYPICAL CONNECTION DIAGRAMS ........................................................................... 27
3.1 Multiplexed Pins ........................................................................................................ 27
3.2 Termination Requirements ........................................................................................ 27
3.3 Phase Locked Loop Filter ......................................................................................... 28
4. POWER ........................................................................................................................... 35
4.1 Decoupling ................................................................................................................ 35
4.2 Analog Power Conditioning ....................................................................................... 35
4.3 Ground ...................................................................................................................... 35
4.4 Pads .......................................................................................................................... 35
5. CLOCKING ..................................................................................................................... 35
6. CONTROL ....................................................................................................................... 36
6.1 Serial Communication ............................................................................................... 36
6.1.1 SPI Communication ...................................................................................... 36
6.1.2 I2C Communication ....................................................................................... 38
6.1.3 INTREQ Behavior: A Special Case .............................................................. 41
6.2 Parallel Host Communication .................................................................................... 44
6.2.1 Intel Parallel Host Communication Mode ...................................................... 46
6.2.2 Motorola Parallel Host Communication Mode .............................................. 47
6.2.3 Procedures for Parallel Host Mode Communication ..................................... 48
7. EXTERNAL MEMORY .................................................................................................... 51
7.1 Non-Paged Memory .................................................................................................. 51
7.2 Paged Memory ......................................................................................................... 52
8. BOOT PROCEDURE & RESET ..................................................................................... 54
8.1 Host Boot .................................................................................................................. 54
8.1.1 Serial Download Sequence .......................................................................... 54
8.1.2 Parallel Download Sequence ........................................................................ 57
8.2 Autoboot .................................................................................................................... 57
8.2.1 Autoboot INTREQ Behavior .......................................................................... 60
8.3 Decreasing Autoboot Times Using GFABT Codes (Fast Autoboot) ......................... 61
8.3.1 Design Considerations when using GFABT Codes ...................................... 63
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Cirrus Logic CS49311
CS49300 Family DSP
8.4 Internal Boot ............................................................................................................. 63
8.5 Application Failure Boot Message ............................................................................ 63
8.6 Resetting the CS493XX ............................................................................................ 63
8.7 External Memory Examples ...................................................................................... 64
8.7.1 Non-Paged Autoboot Memory ...................................................................... 64
8.7.2 32 Kilobyte Paged Autoboot Memory ........................................................... 65
8.8 CDB49300-MEMA.0 ................................................................................................. 66
9. HARDWARE CONFIGURATION ................................................................................... 68
10.DIGITAL INPUT & OUTPUT ........................................................................................... 69
10.1 Digital Audio Formats .............................................................................................. 69
10.1.1 I2S .............................................................................................................. 69
10.1.2 Left Justified ............................................................................................... 69
10.1.3 Multichannel ............................................................................................... 69
10.2 Digital Audio Input Port ........................................................................................... 70
10.3 Compressed Data Input Port ................................................................................... 70
10.4 Byte Wide Digital Audio Data Input ......................................................................... 70
10.4.1 Parallel Delivery with Parallel Control ........................................................ 71
10.4.2 Parallel Delivery with Serial Control ........................................................... 71
10.5 Digital Audio Output Port ......................................................................................... 72
10.5.1 IEC60958 Output ........................................................................................ 73
11.HARDWARE CONFIGURATION ................................................................................... 74
11.1 Address Checking ................................................................................................... 74
11.2 Input Data Hardware Configuration ........................................................................ 74
11.2.1 Input Configuration Considerations ......................................................... 77
11.3 Output Data Hardware Configuration ...................................................................... 78
11.3.1 Output Configuration Considerations ........................................................ 80
11.4 Creating Hardware Configuration Messages .......................................................... 80
12.PIN DESCRIPTIONS ....................................................................................................... 82
13.ORDERING INFORMATION ........................................................................................... 87
14.PACKAGE DIMENSIONS .............................................................................................. 88
15.DOCUMENT REVISIONS ............................................................................................ 89
LIST OF FIGURES
Figure 1. RESET Timing ........................................................................................................ 9
Figure 2. CLKIN with CLKSEL = VSS = PLL Enable ............................................................. 9
Figure 3. Intel® Parallel Host Mode Read Cycle .................................................................. 11
Figure 4. Intel® Parallel Host Mode Write Cycle .................................................................. 11
Figure 5. Motorola® Parallel Host Mode Read Cycle ........................................................... 13
Figure 6. Motorola® Parallel Host Mode Write Cycle ........................................................... 13
Figure 7. SPI Control Port Timing ........................................................................................ 15
Figure 8. I2C® Control Port Timing ...................................................................................... 17
Figure 9. Digital Audio Input Data, Master and Slave Clock Timing ..................................... 19
Figure 10. Serial Compressed Data Timing ......................................................................... 20
Figure 11. Parallel Data Timing (when not in a parallel control mode) ................................. 21
Figure 12. Digital Audio Output Data, Input and Output Clock Timing ................................. 23
Figure 13. I2C® Control ........................................................................................................ 29
Figure 14. I2C® Control with External Memory ..................................................................... 30
Figure 15. SPI Control .......................................................................................................... 31
Figure 16. SPI Control with External Memory ...................................................................... 32
Figure 17. Intel® Parallel Control Mode ................................................................................ 33
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