ADSP-21061 Microcomputer Datasheet

ADSP-21061 Datasheet PDF, Equivalent


Part Number

ADSP-21061

Description

Commercial Grade SHARC DSP Microcomputer

Manufacture

Analog Devices

Total Page 30 Pages
PDF Download
Download ADSP-21061 Datasheet PDF


ADSP-21061
a
SUMMARY
High performance signal processor for communications,
graphics, and imaging applications
Super Harvard Architecture
Four independent buses for dual data fetch, instruction
fetch, and nonintrusive I/O
32-bit IEEE floating-point computation units—multiplier,
ALU, and shifter
Dual-ported on-chip SRAM and integrated I/O peripherals—a
complete system-on-a-chip
Integrated multiprocessing features
KEY FEATURES—PROCESSOR CORE
50 MIPS, 20 ns instruction rate, single-cycle instruction
execution
120 MFLOPS peak, 80 MFLOPS sustained performance
Commercial Grade
SHARC DSP Microcomputer
ADSP-21061/ADSP-21061L
Dual data address generators with modulo and bit-reverse
addressing
Efficient program sequencing with zero-overhead looping:
single-cycle loop setup
IEEE JTAG Standard 1149.1 test access port and on-chip
emulation
32-bit single-precision and 40-bit extended-precision IEEE
floating-point data formats or 32-bit fixed-point data
format
240-lead MQFP package, thermally enhanced MQFP, 225-ball
plastic ball grid array (PBGA)
Lead (Pb) free packages. For more information, see Ordering
Guide on Page 52.
CORE PROCESSOR
TIMER
INSTRUCTION
CACHE
32 ϫ 48-BIT
DAG1
DAG2
8 ϫ 4 ϫ 32 8 ϫ 4 ϫ 24
PROGRAM
SEQUENCER
PM ADDRESS BUS
DM ADDRESS BUS
24
32
BUS
CONNECT
(PX)
PM DATA BUS
48
DM DATA BUS 40/32
DUAL-PORTED SRAM
TWO INDEPENDENT
DUAL-PORTED BLOCKS
PROCESSOR PORT
I/O PORT
ADDR
DATA
DATA
ADDR
ADDR
DATA
DATA
ADDR
IOD IOA
48 17
S
JTAG
TEST AND
EMULATION
7
EXTERNAL
PORT
ADDR BUS
MUX
32
MULTIPROCESSOR
INTERFACE
DATA BUS
MUX
48
HOST PORT
DATA
REGISTER
FILE
MULT 16 ϫ 40-BIT
BARREL
SHIFTER
ALU
IOP
REGISTERS
(MEMORY
MAPPED)
CONTROL,
STATUS AND
DATA BUFFERS
DMA
CONTROLLER
SERIAL PORTS
(2)
4
6
6
I/O PROCESSOR
Figure 1. Functional Block Diagram
SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
Rev. D
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781.329.4700
©2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com

ADSP-21061
ADSP-21061/ADSP-21061L
TABLE OF CONTENTS
Summary ............................................................... 1
Key Features—Processor Core ................................. 1
General Description ................................................. 3
SHARC Family Core Architecture ............................ 3
Memory and I/O Interface Features ........................... 4
Porting Code From the ADSP-21060 or
ADSP-21062 ..................................................... 7
Development Tools ............................................... 7
Additional Information .......................................... 8
Related Signal Chains ............................................ 8
Pin Function Descriptions ......................................... 9
Target Board Connector For EZ-ICE Probe ............... 12
ADSP-21061 Specifications ...................................... 14
Operating Conditions (5 V) ................................... 14
Electrical Characteristics (5 V) ............................... 14
Internal Power Dissipation (5 V) ............................ 15
External Power Dissipation (5 V) ............................ 16
REVISION HISTORY
5/13—Rev C to Rev D
Updated Development Tools .......................................7
Added Related Signal Chains .......................................8
Removed the ADSP-21061LAS-176, ADSP-21061LKS-160, and
ADSP-21061LKS-176 models from Ordering Guide ........ 52
GENERAL NOTE
This data sheet represents production released specifications for
the ADSP-21061 (5 V) and ADSP-21061L (3.3 V) processors for
33 MHz, 40 MHz, 44 MHz, and 50 MHz speed grades. The
product name“ADSP-21061” is used throughout this data sheet
to represent all devices, except where expressly noted.
ADSP-21061L Specifications ..................................... 17
Operating Conditions (3.3 V) ................................. 17
Electrical Characteristics (3.3 V) ............................. 17
Internal Power Dissipation (3.3 V) .......................... 18
External Power Dissipation (3.3 V) .......................... 19
Absolute Maximum Ratings ................................... 20
ESD Caution ...................................................... 20
Package Marking Information ................................ 20
Timing Specifications ........................................... 20
Test Conditions .................................................. 43
Environmental Conditions .................................... 46
225-Ball PBGA Pin Configurations ............................. 47
240-Lead MQFP Pin Configurations ........................... 49
Outline Dimensions ................................................ 50
Surface-Mount Design .......................................... 52
Ordering Guide ..................................................... 52
Rev. D | Page 2 of 52 | May 2013


Features a SUMMARY High performance signal proces sor for communications, graphics, and i maging applications Super Harvard Archi tecture Four independent buses for dual data fetch, instruction fetch, and non intrusive I/O 32-bit IEEE floating-poin t computation units—multiplier, ALU, and shifter Dual-ported on-chip SRAM an d integrated I/O peripherals—a comple te system-on-a-chip Integrated multipro cessing features KEY FEATURES—PROCESS OR CORE 50 MIPS, 20 ns instruction rate , single-cycle instruction execution 12 0 MFLOPS peak, 80 MFLOPS sustained perf ormance Commercial Grade SHARC DSP Mic rocomputer ADSP-21061/ADSP-21061L Dual data address generators with modulo and bit-reverse addressing Efficient progr am sequencing with zero-overhead loopin g: single-cycle loop setup IEEE JTAG St andard 1149.1 test access port and on-c hip emulation 32-bit single-precision a nd 40-bit extended-precision IEEE float ing-point data formats or 32-bit fixed- point data format 240-lead MQFP package, thermally enhanced MQFP, 225.
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