DSP Microcomputer. ADSP-21061L Datasheet

ADSP-21061L Microcomputer. Datasheet pdf. Equivalent

ADSP-21061L Datasheet
Recommendation ADSP-21061L Datasheet
Part ADSP-21061L
Description Commercial Grade SHARC DSP Microcomputer
Feature ADSP-21061L; a SUMMARY High performance signal processor for communications, graphics, and imaging applications S.
Manufacture Analog Devices
Datasheet
Download ADSP-21061L Datasheet





Analog Devices ADSP-21061L
a
SUMMARY
High performance signal processor for communications,
graphics, and imaging applications
Super Harvard Architecture
Four independent buses for dual data fetch, instruction
fetch, and nonintrusive I/O
32-bit IEEE floating-point computation units—multiplier,
ALU, and shifter
Dual-ported on-chip SRAM and integrated I/O peripherals—a
complete system-on-a-chip
Integrated multiprocessing features
KEY FEATURES—PROCESSOR CORE
50 MIPS, 20 ns instruction rate, single-cycle instruction
execution
120 MFLOPS peak, 80 MFLOPS sustained performance
Commercial Grade
SHARC DSP Microcomputer
ADSP-21061/ADSP-21061L
Dual data address generators with modulo and bit-reverse
addressing
Efficient program sequencing with zero-overhead looping:
single-cycle loop setup
IEEE JTAG Standard 1149.1 test access port and on-chip
emulation
32-bit single-precision and 40-bit extended-precision IEEE
floating-point data formats or 32-bit fixed-point data
format
240-lead MQFP package, thermally enhanced MQFP, 225-ball
plastic ball grid array (PBGA)
Lead (Pb) free packages. For more information, see Ordering
Guide on Page 52.
CORE PROCESSOR
TIMER
INSTRUCTION
CACHE
32 ϫ 48-BIT
DAG1
DAG2
8 ϫ 4 ϫ 32 8 ϫ 4 ϫ 24
PROGRAM
SEQUENCER
PM ADDRESS BUS
DM ADDRESS BUS
24
32
BUS
CONNECT
(PX)
PM DATA BUS
48
DM DATA BUS 40/32
DUAL-PORTED SRAM
TWO INDEPENDENT
DUAL-PORTED BLOCKS
PROCESSOR PORT
I/O PORT
ADDR
DATA
DATA
ADDR
ADDR
DATA
DATA
ADDR
IOD IOA
48 17
S
JTAG
TEST AND
EMULATION
7
EXTERNAL
PORT
ADDR BUS
MUX
32
MULTIPROCESSOR
INTERFACE
DATA BUS
MUX
48
HOST PORT
DATA
REGISTER
FILE
MULT 16 ϫ 40-BIT
BARREL
SHIFTER
ALU
IOP
REGISTERS
(MEMORY
MAPPED)
CONTROL,
STATUS AND
DATA BUFFERS
DMA
CONTROLLER
SERIAL PORTS
(2)
4
6
6
I/O PROCESSOR
Figure 1. Functional Block Diagram
SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
Rev. D
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Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781.329.4700
©2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com



Analog Devices ADSP-21061L
ADSP-21061/ADSP-21061L
TABLE OF CONTENTS
Summary ............................................................... 1
Key Features—Processor Core ................................. 1
General Description ................................................. 3
SHARC Family Core Architecture ............................ 3
Memory and I/O Interface Features ........................... 4
Porting Code From the ADSP-21060 or
ADSP-21062 ..................................................... 7
Development Tools ............................................... 7
Additional Information .......................................... 8
Related Signal Chains ............................................ 8
Pin Function Descriptions ......................................... 9
Target Board Connector For EZ-ICE Probe ............... 12
ADSP-21061 Specifications ...................................... 14
Operating Conditions (5 V) ................................... 14
Electrical Characteristics (5 V) ............................... 14
Internal Power Dissipation (5 V) ............................ 15
External Power Dissipation (5 V) ............................ 16
REVISION HISTORY
5/13—Rev C to Rev D
Updated Development Tools .......................................7
Added Related Signal Chains .......................................8
Removed the ADSP-21061LAS-176, ADSP-21061LKS-160, and
ADSP-21061LKS-176 models from Ordering Guide ........ 52
GENERAL NOTE
This data sheet represents production released specifications for
the ADSP-21061 (5 V) and ADSP-21061L (3.3 V) processors for
33 MHz, 40 MHz, 44 MHz, and 50 MHz speed grades. The
product name“ADSP-21061” is used throughout this data sheet
to represent all devices, except where expressly noted.
ADSP-21061L Specifications ..................................... 17
Operating Conditions (3.3 V) ................................. 17
Electrical Characteristics (3.3 V) ............................. 17
Internal Power Dissipation (3.3 V) .......................... 18
External Power Dissipation (3.3 V) .......................... 19
Absolute Maximum Ratings ................................... 20
ESD Caution ...................................................... 20
Package Marking Information ................................ 20
Timing Specifications ........................................... 20
Test Conditions .................................................. 43
Environmental Conditions .................................... 46
225-Ball PBGA Pin Configurations ............................. 47
240-Lead MQFP Pin Configurations ........................... 49
Outline Dimensions ................................................ 50
Surface-Mount Design .......................................... 52
Ordering Guide ..................................................... 52
Rev. D | Page 2 of 52 | May 2013



Analog Devices ADSP-21061L
GENERAL DESCRIPTION
The ADSP-21061 SHARC—Super Harvard Architecture Com-
puter—is a signal processing microcomputer that offers new
capabilities and levels of performance. The ADSP-21061
SHARC is a 32-bit processor optimized for high performance
DSP applications. The ADSP-21061 builds on the ADSP-21000
DSP core to form a complete system-on-a-chip, adding a dual-
ported on-chip SRAM and integrated I/O peripherals supported
by a dedicated I/O bus.
Fabricated in a high speed, low power CMOS process, the
ADSP-21061 has a 20 ns instruction cycle time and operates at
50 MIPS. With its on-chip instruction cache, the processor can
execute every instruction in a single cycle. Table 1 shows perfor-
mance benchmarks for the ADSP-21061/ADSP-21061L.
The ADSP-21061 SHARC represents a new standard of integra-
tion for signal computers, combining a high performance
floating-point DSP core with integrated, on-chip system fea-
tures including 1M bit SRAM memory, a host processor
interface, a DMA controller, serial ports, and parallel bus con-
nectivity for glueless DSP multiprocessing.
Table 1. Benchmarks (at 50 MHz)
Benchmark Algorithm
1024 Point Complex FFT (Radix 4,
with reversal)
FIR Filter (per tap)
IIR Filter (per biquad)
Divide (y/x)
Inverse Square Root
DMA Transfer Rate
Speed
.37 ms
Cycles
18,221
20 ns
80 ns
120 ns
180 ns
300M bps
1
4
6
9
The ADSP-21061 continues SHARC’s industry-leading stan-
dards of integration for DSPs, combining a high performance
32-bit DSP core with integrated, on-chip system features.
The block diagram on Page 1, illustrates the following architec-
tural features:
• Computation units (ALU, multiplier, and shifter) with a
shared data register file
• Data address generators (DAG1, DAG2)
• Program sequencer with instruction cache
• PM and DM buses capable of supporting four 32-bit data
transfers between memory and the core at every core pro-
cessor cycle
• Interval timer
• On-chip SRAM
• External port for interfacing to off-chip memory and
peripherals
• Host port and multiprocessor interface
• DMA controller
ADSP-21061/ADSP-21061L
• Serial ports
• JTAG test access port
1 ϫ CLOCK
TO GND
3
4
SERIAL
DEVICE
(OPTIONAL)
SERIAL
DEVICE
(OPTIONAL)
ADSP-21061
CLKIN
EBOOT
LBOOT
IRQ2–0
FLAG3–0
TIMEXP
TCLK0
RCLK0
TFS0
RSF0
DT0
DR0
TCLK1
RCLK1
TFS1
RSF1
DT1
DR1
BMS
ADDR31–0
DATA47–0
RD
WR
ACK
MS3–0
PAGE
SW
SBTS
ADRCLK
DMAR1–2
DMAG1–2
CS
HBR
HBG
REDY
RPBA
ID2–0
RESET
BR1–6
CPA
JTAG
7
CS BOOT
ADDR EPROM
DATA (OPTIONAL)
ADDR
DATA MEMORY-
OE
MAPPED
DEVICES
WE (OPTIONAL)
ACK
CS
DMA DEVICE
(OPTIONAL)
DATA
HOST
PROCESSOR
INTERFACE
(OPTIONAL)
ADDR
DATA
Figure 2. ADSP-21061/ADSP-21061L System Sample Configuration
SHARC FAMILY CORE ARCHITECTURE
The ADSP-21061 includes the following architectural features
of the ADSP-21000 family core. The ADSP-21061 processors
are code- and function-compatible with the ADSP-21020,
ADSP-21060, and ADSP-21062 SHARC processors.
Independent, Parallel Computation Units
The arithmetic/logic unit (ALU), multiplier, and shifter all per-
form single-cycle instructions. The three units are arranged in
parallel, maximizing computational throughput. Single multi-
function instructions execute parallel ALU and multiplier oper-
ations. These computation units support IEEE 32-bit single-
precision floating-point, extended-precision 40-bit floating-
point, and 32-bit fixed-point data formats.
Data Register File
A general-purpose data register file is used for transferring data
between the computation units and the data buses, and for stor-
ing intermediate results. This 10-port, 32-register (16 primary,
16 secondary) register file, combined with the ADSP-21000
Harvard architecture, allows unconstrained data flow between
computation units and internal memory.
Rev. D | Page 3 of 52 | May 2013





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