FLASH MEMORY. A28F200BX-B Datasheet

A28F200BX-B MEMORY. Datasheet pdf. Equivalent

A28F200BX-B Datasheet
Recommendation A28F200BX-B Datasheet
Part A28F200BX-B
Description 2-MBIT BOOT BLOCK FLASH MEMORY
Feature A28F200BX-B; A28F200BX-T B 2-MBIT (128K x 16 256K x 8) BOOT BLOCK FLASH MEMORY FAMILY Automotive Y x8 x16 Input .
Manufacture Intel
Datasheet
Download A28F200BX-B Datasheet





Intel A28F200BX-B
A28F200BX-T B
2-MBIT (128K x 16 256K x 8) BOOT BLOCK
FLASH MEMORY FAMILY
Automotive
Y x8 x16 Input Output Architecture
A28F200BX-T A28F200BX-B
For High Performance and High
Integration 16-bit and 32-bit CPUs
Y Optimized High Density Blocked
Architecture
One 16 KB Protected Boot Block
Two 8 KB Parameter Blocks
One 96 KB Main Block
One 128 KB Main Block
Top or Bottom Boot Locations
Y Extended Cycling Capability
1 000 Block Erase Cycles
Y Automated Word Byte Write and
Block Erase
Command User Interface
Status Register
Erase Suspend Capability
Y SRAM-Compatible Write Interface
Y Automatic Power Savings Feature
1 mA Typical ICC Active Current in
Static Operation
Y Hardware Data Protection Feature
Erase Write Lockout during Power
Transitions
Y Very High-Performance Read
90 ns Maximum Access Time
45 ns Maximum Output Enable Time
Y Low Power Consumption
25 mA Typical Active Read Current
Y Deep Power-Down Reset Input
Acts as Reset for Boot Operations
Y Automotive Temperature Operation
b40 C to a125 C
Y Write Protection for Boot Block
Y Industry Standard Surface Mount
Packaging
JEDEC ROM Compatible
44-Lead PSOP
Y 12V Word Byte Write and Block Erase
VPP e 12V g5% Standard
Y ETOXTM III Flash Technology
5V Read
Y Independent Software Vendor Support
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT INTEL CORPORATION 1995
November 1995
Order Number 290500-003



Intel A28F200BX-B
A28F200BX-T B
Intel’s 2-Mbit Flash Memory Family is an extension of the Boot Block Architecture which includes block-selec-
tive erasure automated write and erase operations and standard microprocessor interface The 2 Mbit Flash
Memory Family enhances the Boot Block Architecture by adding more density and blocks x8 x16 input out-
put control very high speed low power an industry standard ROM compatible pinout The 2-Mbit flash family
allows for an easy upgrade to Intel’s 4-Mbit Boot Block Flash Memory Family
The Intel A28F200BX-T B are 16-bit wide flash memory offerings optimized to meet the rigorous environmen-
tal requirements of Automotive Applications These high density flash memories provide user selectable bus
operation for either 8-bit or 16-bit applications The A28F200BX-T and A28F200BX-B are 2 097 152-bit non-
volatile memories organized as either 262 144 bytes or 131 072 words of information They are offered in 44-
Lead plastic SOP packages The x8 x16 pinout conforms to the industry standard ROM EPROM pinout Read
and Write Characteristics are guaranteed over the ambient temperature range of b40 C to a125 C
These devices use an integrated Command User Interface (CUI) and Write State Machine (WSM) for simplified
word byte write and block erasure The A28F200BX-T provides block locations compatible with Intel’s
MCS-186 family 80286 i386TM i486TM i860TM and 80960CA microprocessors The A28F200BX-B provides
compatibility with Intel’s 80960KX and 80960SX families as well as other embedded microprocessors
The boot block includes a data protection feature to protect the boot code in critical applications With a
maximum access time of 90 ns these 2 Mbit flash devices are very high performance memories which
interface at zero-wait-state to a wide range of microprocessors and microcontrollers
Manufactured on Intel’s 0 8 micron ETOXTM III process the 2-Mbit flash memory family provides world class
quality reliability and cost-effectiveness at the 2-Mbit density level
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Intel A28F200BX-B
A28F200BX-T B
1 0 PRODUCT FAMILY OVERVIEW
Throughout this datasheet the A28F200BX refers to
both the A28F200BX-T and A28F200BX-B devices
Section 1 provides an overview of the 2-Mbit flash
memory family including applications pinouts and
pin descriptions Section 2 describes in detail the
specific memory organization Section 3 provides a
description of the family’s principles of operation Fi-
nally the family’s operating specifications are de-
scribed
1 1 Main Features
The A28F200BX boot block flash memory family is a
very high performance 2-Mbit (2 097 152 bit) memo-
ry family organized as either 128-KWords (131 072
words) of 16 bits each or 256-Kbytes (262 144
bytes) of 8 bits each
Five Separately Erasable Blocks including a hard-
ware-lockable boot block (16 384 Bytes) two pa-
rameter blocks (8 192 Bytes each) and two main
blocks (1 block of 98 304 Bytes and 1 block of
131 072 Bytes) are included on the 2-Mbit family An
erase operation erases one of the main blocks in
typically 3 seconds and the boot or parameter
blocks in typically 1 5 seconds Each block can be
independently erased and programmed 1 000 times
The Boot Block is located at either the top
(A28F200BX-T) or the bottom (A28F200BX-B) of the
address map in order to accommodate different mi-
croprocessor protocols for boot code location The
hardware lockable boot block provides the most
secure code storage The boot block is intended to
store the kernel code required for booting-up a sys-
tem When the RP pin is between 11 4V and 12 6V
the boot block is unlocked and program and erase
operations can be performed When the RP pin is
at or below 6 5V the boot block is locked and pro-
gram and erase operations to the boot block are
ignored
The A28F200BX products are available in the ROM
EPROM compatible pinout and housed in the
44-Lead PSOP (Plastic Small Outline) package as
shown in Figure 3
The Command User Interface (CUI) serves as the
interface between the microprocessor or microcon-
troller and the internal operation of the A28F200BX
flash memory
Program and Erase Automation allows program
and erase operations to be executed using a two-
write command sequence to the CUI The internal
Write State Machine (WSM) automatically executes
the algorithms and timings necessary for program
and erase operations including verifications there-
by unburdening the microprocessor or microcontrol-
ler Writing of memory data is performed in word or
byte increments for the A28F200BX family typically
within 9 ms which is a 100% improvement over pre-
vious flash memory products
The Status Register (SR) indicates the status of the
WSM and whether the WSM successfully completed
the desired program or erase operation
Maximum Access Time of 90 ns (TACC) is achieved
over the automotive temperature range (b40 C to
125 C) 10% VCC supply voltage range and 100 pF
output load
IPP maximum Program current is 40 mA for x16
operation and 30 mA for x8 operation IPP Erase
current is 30 mA maximum VPP erase and pro-
gramming voltage is 11 4V to 12 6V (VPP e 12V
g5%) under all operating conditions Typical ICC
Active Current of 25 mA is achieved
The 2-Mbit boot block flash family is also designed
with an Automatic Power Savings (APS) feature to
minimize system battery current drain and allow for
very low power designs Once the device is ac-
cessed to read array data APS mode will immedi-
ately put the memory in static mode of operation
where ICC active current is typically 1 mA until the
next read is initiated
When the CE and RP pins are at VCC and the
BYTE pin is at either VCC or GND the CMOS
Standby mode is enabled where ICC is typically
80 mA
A Deep Power-Down Mode is enabled when the
RP pin is at ground minimizing power consumption
and providing write protection during power-up con-
ditions ICC current during deep power-down mode
is 50 mA typical An initial maximum access time or
Reset Time of 300 ns is required from RP switch-
ing until outputs are valid Equivalently the device
has a maximum wake-up time of 210 ns until writes
to the Command User Interface are recognized
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