XC3S400AN

1 Spartan-3AN FPGA Family Data Sheet DS557 January 9, 2019 Product Specification Module 1: Introduction and Ordering Information DS557(v4.3) January 9, 2019 Introduction Features Architectural Overview Configuration Overview In-system Flash Memory Overview General I/O Capabilities Supported Packages and Package Marking Ordering Information Module 2: Functional Description DS557 (v4.3) January 9, 2019 The functionality of the Spartan®-3AN FPGA family is described in the following documents: UG331: Spartan-3 Generation FPGA User Guide Clocking Resources Digital Clock Managers (DCMs) Block RAM Configurable Logic Blocks (CLBs) - Distributed RAM - SRL16 Shift Registers - Carry and Arithmetic Logic I/O Resources Embedded Multiplier Blocks Programmable Interconnect ISE® Design Tools and IP Cores Embedded Processing and Control Solutions Pin Types and Package Overview Package Drawings Powering FPGAs Power Management UG332: Spartan-3 Generation Configuration User Guide Configuration Overview Configuration Pins and Behavior Bitstream Sizes Detailed Descriptions by Mode - Self-contained In-System Flash mode - Master Serial Mode using Platform Flash PROM - Master SPI Mode using Commodity Serial Flash - Master BPI Mode using Commodity Parallel Flash - Slave Parallel (SelectMAP) using a Processor - Slave Serial using a Processor - JTAG Mode ISE iMPACT Programming Examples MultiBoot Reconfiguration Design Authentication using De...