Spartan-3AN FPGA. XC3S700AN Datasheet

XC3S700AN FPGA. Datasheet pdf. Equivalent

XC3S700AN Datasheet
Recommendation XC3S700AN Datasheet
Part XC3S700AN
Description Spartan-3AN FPGA
Feature XC3S700AN; 1 Spartan-3AN FPGA Family Data Sheet DS557 January 9, 2019 Product Specification Module 1: Introd.
Manufacture Xilinx
Download XC3S700AN Datasheet

Xilinx XC3S700AN
Spartan-3AN FPGA Family Data Sheet
DS557 January 9, 2019
Product Specification
Module 1:
Introduction and Ordering Information
DS557(v4.3) January 9, 2019
• Introduction
• Features
• Architectural Overview
• Configuration Overview
• In-system Flash Memory Overview
• General I/O Capabilities
• Supported Packages and Package Marking
• Ordering Information
Module 2:
Functional Description
DS557 (v4.3) January 9, 2019
The functionality of the Spartan®-3AN FPGA family is
described in the following documents:
UG331: Spartan-3 Generation FPGA User Guide
• Clocking Resources
• Digital Clock Managers (DCMs)
• Block RAM
• Configurable Logic Blocks (CLBs)
- Distributed RAM
- SRL16 Shift Registers
- Carry and Arithmetic Logic
• I/O Resources
• Embedded Multiplier Blocks
• Programmable Interconnect
• ISE® Design Tools and IP Cores
• Embedded Processing and Control Solutions
• Pin Types and Package Overview
• Package Drawings
• Powering FPGAs
• Power Management
UG332: Spartan-3 Generation Configuration User Guide
• Configuration Overview
• Configuration Pins and Behavior
• Bitstream Sizes
• Detailed Descriptions by Mode
- Self-contained In-System Flash mode
- Master Serial Mode using Platform Flash PROM
- Master SPI Mode using Commodity Serial Flash
- Master BPI Mode using Commodity Parallel Flash
- Slave Parallel (SelectMAP) using a Processor
- Slave Serial using a Processor
- JTAG Mode
• ISE iMPACT Programming Examples
• MultiBoot Reconfiguration
• Design Authentication using Device DNA
UG333: Spartan-3AN In-System Flash User Guide
UG334: Spartan-3AN Starter Kit User Guide
Module 3:
DC and Switching Characteristics
DS557 (v4.3) January 9, 2019
• DC Electrical Characteristics
• Absolute Maximum Ratings
• Supply Voltage Specifications
• Recommended Operating Conditions
• Switching Characteristics
• I/O Timing
• Configurable Logic Block (CLB) Timing
• Multiplier Timing
• Block RAM Timing
• Digital Clock Manager (DCM) Timing
• Suspend Mode Timing
• Device DNA Timing
• Configuration and JTAG Timing
Module 4:
Pinout Descriptions
DS557 (v4.3) January 9, 2019
• Pin Descriptions
• Package Overview
• Pinout Tables
• Footprint Diagrams
Table 1: Production Status of Spartan-3AN FPGAs
Spartan-3AN FPGA
Additional information on the Spartan-3AN family can be
found at:
© Copyright 2007–2019 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx
in the United States and other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.
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Product Specification
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Xilinx XC3S700AN
Spartan-3AN FPGA Family:
Introduction and Ordering Information
DS557(v4.3) January 9, 2019
Product Specification
The Spartan®-3AN FPGA family combines the best attributes of a
leading edge, low cost FPGA with nonvolatile technology across a
broad range of densities. The family combines all the features of
the Spartan-3A FPGA family plus leading technology in-system
Flash memory for configuration and nonvolatile data storage.
The Spartan-3AN FPGAs are part of the Extended Spartan-3A
family, which also includes the Spartan-3A FPGAs and the higher
density Spartan-3A DSP FPGAs. The Spartan-3AN FPGA family
is excellent for space-constrained applications such as blade
servers, medical devices, automotive infotainment, telematics,
GPS, and other small consumer products. Combining FPGA and
Flash technology minimizes chip count, PCB traces and overall
size while increasing system reliability.
The Spartan-3AN FPGA internal configuration interface is
completely self-contained, increasing design security. The family
maintains full support for external configuration. The Spartan-3AN
FPGA is the world’s first nonvolatile FPGA with MultiBoot,
supporting two or more configuration files in one device, allowing
alternative configurations for field upgrades, test modes, or
multiple system configurations.
• The new standard for low cost nonvolatile FPGA solutions
• Eliminates traditional nonvolatile FPGA limitations with the
advanced 90 nm Spartan-3A device feature set
• Memory, multipliers, DCMs, SelectIO, hot swap, power
management, etc.
• Integrated robust configuration memory
• Saves board space
• Improves ease-of-use
• Simplifies design
• Reduces support issues
• Plentiful amounts of nonvolatile memory available to the user
• Up to 11+ Mb available
• MultiBoot support
• Embedded processing and code shadowing
• Scratchpad memory
• Robust 100K Flash memory program/erase cycles
• 20 years Flash memory data retention
• Security features provide bitstream anti-cloning protection
• Buried configuration interface
• Unique Device DNA serial number in each device for
design Authentication to prevent unauthorized copying
• Flash memory sector protection and lockdown
• Configuration watchdog timer automatically recovers from
configuration errors
• Suspend mode reduces system power consumption
• Retains all design state and FPGA configuration data
• Fast response time, typically less than 100 μs
• Full hot-swap compliance
• Multi-voltage, multi-standard SelectIO™ interface pins
• Up to 502 I/O pins or 227 differential signal pairs
• LVCMOS, LVTTL, HSTL, and SSTL single-ended signal
• 3.3V, 2.5V, 1.8V, 1.5V, and 1.2V signaling
• Up to 24 mA output drive
• 3.3V ±10% compatibility and hot swap compliance
• 622+ Mb/s data transfer rate per I/O
• DDR/DDR2 SDRAM support up to 400 Mb/s
differential I/O
• Abundant, flexible logic resources
• Densities up to 25,344 logic cells
• Optional shift register or distributed RAM support
• Enhanced 18 x 18 multipliers with optional pipeline
• Hierarchical SelectRAM™ memory architecture
• Up to 576 Kbits of dedicated block RAM
• Up to 176 Kbits of efficient distributed RAM
• Up to eight Digital Clock Managers (DCMs)
• Eight global clocks and eight additional clocks per each half
of device, plus abundant low-skew routing
• Complete Xilinx® ISE® and WebPACK™ software
development system support
MicroBlaze™ and PicoBlazeembedded processor cores
• Fully compliant 32-/64-bit 33 MHz PCI™ technology support
• Low-cost QFP and BGA Pb-free (RoHS) packaging options
• Pin-compatible with the same packages in the
Spartan-3A FPGA family
Table 2: Summary of Spartan-3AN FPGA Attributes
System Equivalent
Device Gates Logic Cells
XC3S50AN 50K
XC3S200AN 200K 4,032
XC3S400AN 400K 8,064
XC3S700AN 700K 13,248
XC3S1400AN 1400K 25,344
Distributed Block RAM Dedicated
Maximum Max Differential Bitstream In-System
RAM Bits(1) Bits(1) Multipliers DCMs User I/O
I/O Pairs
Size(1) Flash Bits
11K 54K
3 2 108
28K 288K
16 4 195
56K 360K
20 4 311
92K 360K
20 8 372
32 8 502
227 4,644K 16M
1. By convention, one Kb is equivalent to 1,024 bits and one Mb is equivalent to 1,024 Kb.
2. Maximum supported by Xilinx tools. See the customer notice XCN14003: Flash Wafer Fabrication Change and Gold (Au) To Copper (Cu) Transition
for Spartan-3AN FPGA Devices.
© Copyright 2007–2019 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx
in the United States and other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.
DS557(v4.3) January 9, 2019
Product Specification
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Xilinx XC3S700AN
Spartan-3AN FPGA Family: Introduction and Ordering Information
Architectural Overview
The Spartan-3AN FPGA architecture is compatible with that
of the Spartan-3A FPGA. The architecture consists of five
fundamental programmable functional elements:
Configurable Logic Blocks (CLBs) contain flexible
Look-Up Tables (LUTs) that implement logic plus
storage elements used as flip-flops or latches.
Input/Output Blocks (IOBs) control the flow of data
between the I/O pins and the internal logic of the
device. IOBs support bidirectional data flow plus
3-state operation. They support a variety of signal
standards, including several high-performance
differential standards. Double Data-Rate (DDR)
registers are included.
Block RAM provides data storage in the form of
18-Kbit dual-port blocks.
Multiplier Blocks accept two 18-bit binary numbers as
inputs and calculate the product.
X-Ref Target - Figure 1
Digital Clock Manager (DCM) Blocks provide
self-calibrating, fully digital solutions for distributing,
delaying, multiplying, dividing, and phase-shifting clock
These elements are organized as shown in Figure 1. A dual
ring of staggered IOBs surrounds a regular array of CLBs.
Each device has two columns of block RAM except for the
XC3S50AN, which has one column. Each RAM column
consists of several 18-Kbit RAM blocks. Each block RAM is
associated with a dedicated multiplier. The DCMs are
positioned in the center with two at the top and two at the
bottom of the device. The XC3S50AN has DCMs only at the
top, while the XC3S700AN and XC3S1400AN add two
DCMs in the middle of the two columns of block RAM and
The Spartan-3AN FPGA features a rich network of traces
that interconnect all five functional elements, transmitting
signals among them. Each functional element has an
associated switch matrix that permits multiple connections
to the routing.
1. The XC3S700AN and XC3S1400AN have two additional DCMs on both the left and right sides as indicated by the
dashed lines. The XC3S50AN has only two DCMs at the top and only one Block RAM/Multiplier column.
Figure 1: Spartan-3AN Family Architecture
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