Document
January 2003, ver. 11.1
®
FLEX 8000
Programmable Logic Device Family
Data Sheet
1
Features...
■ Low-cost, high-density, register-rich CMOS programmable logic device (PLD) family (see Table 1) – 2,500 to 16,000 usable gates – 282 to 1,500 registers
■ System-level features – In-circuit reconfigurability (ICR) via external configuration devices or intelligent controller – Fully compliant with the peripheral component interconnect Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2 for 5.0-V operation – Built-in Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990 on selected devices – MultiVoltTM I/O interface enabling device core to run at 5.0 V, while I/O pins are compatible with 5.0-V and 3.3-V logic levels – Low power consumption (typical specification is 0.5 mA or less in standby mode)
■ Flexible interconnect – FastTrack® Interconnect continuous routing structure for fast, predictable interconnect delays – Dedicated carry chain that implements arithmetic functions such as fast adders, counters, and comparators (automatically used by software tools and megafunctions) – Dedicated cascade chain that implements high-speed, high-fan-in logic functions (automatically used by software tools and megafunctions) – Tri-state emulation that implements internal tri-state nets
■ Powerful I/O pins ■ Programmable output slew-rate control reduces switching noise
Table 1. FLEX 8000 Device Features
Feature
EPF8282A EPF8452A EPF8282AV
Usable gates
2,500
4,000
Flipflops
282 452
Logic array blocks (LABs)
26
42
Logic elements (LEs)
208 336
Maximum user I/O pins
78
120
EPF8636A
6,000 636 63 504 136
EPF8820A EPF81188A EPF81500A
8,000 820 84 672 152
12,000 1,188 126 1,008 184
16,000 1,500 162 1,296 208
FLEX 8000
3
Altera Corporation
DS-F8000-11.1
1
FLEX 8000 Programmable Logic Device Family Data Sheet
JTAG BST circuitry
...and More Features
Yes No Yes Yes No Yes
■ Peripheral register for fast setup and clock-to-output delay ■ Fabricated on an advanced SRAM process ■ Available in a variety of packages with 84 to 304 pins (see Table 2) ■ Software design support and automatic place-and-route provided by
the Altera® MAX+PLUS® II development system for Windows-based PCs, as well as Sun SPARCstation, HP 9000 Series 700/800, and IBM RISC System/6000 workstations ■ Additional design entry and simulation support provided by EDIF 2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM), Verilog HDL, VHDL, and other interfaces to popular EDA tools from manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity, and Veribest
Table 2. FLEX 8000 Package Options & I/O Pin Count Note (1)
Device
84- 100- 144- 160- 160- 192- 208- 225- 232- 240- 280- 304Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin PLCC TQFP TQFP PQFP PGA PGA PQFP BGA PGA PQFP PGA RQFP
EPF8282A EPF8282AV EPF8452A EPF8636A EPF8820A EPF81188A EPF81500A
68
68 68
78
78.