Spartan-IIE FPGA
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R Spartan-IIE FPGA Family
Data Sheet
DS077 August 9, 2013
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Description
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0
R Spartan-IIE FPGA Family
Data Sheet
DS077 August 9, 2013
0 0 Product Specification
This document includes all four modules of the Spartan®-IIE FPGA data sheet.
Module 1: Introduction and Ordering Information
DS077-1 (v3.0) August 9, 2013
Introduction Features General Overview Product Availability User I/O Chart Ordering Information
Module 2: Functional Description
DS077-2 (v3.0) August 9, 2013
Architectural Description - Spartan-IIE Array - Input/Output Block - Configurable Logic Block - Block RAM - Clock Distribution: Delay-Locked Loop - Boundary Scan
Development System Configuration
Module 3: DC and Switching Characteristics
DS077-3 (v3.0) August 9, 2013
DC Specifications - Absolute Maximum Ratings - Recommended Operating Conditions - DC Characteristics - Power-On Requirements - DC Input and Output Levels
Switching Characteristics - Pin-to-Pin Parameters - IOB Switching Characteristics - Clock Distribution Characteristics - DLL Timing Parameters - CLB Switching Characteristics - Block RAM Switching Characteristics - TBUF Switching Characteristics - JTAG Switching Characteristics - Configuration Switching Characteristics
Module 4: Pinout Tables
DS077-4 (v3.0) August 9, 2013
Pin Definitions Pinout Tables
IMPORTANT NOTE: The Spartan-IIE FPGA data sheet is in four modules. Each module has its own Revision History at the end. Use the PDF "Bookmarks" for easy navigation in this volume.
© 2001–2013 ...
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