XC4013 Array Datasheet

XC4013 Datasheet PDF, Equivalent


Part Number

XC4013

Description

Logic Cell Array

Manufacture

Xilinx

Total Page 30 Pages
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Download XC4013 Datasheet PDF


XC4013
® XC4000, XC4000A, XC4000H
Logic Cell Array Families
Product Description
Features
Description
Third Generation Field-Programmable Gate Arrays
– Abundant flip-flops
– Flexible function generators
– On-chip ultra-fast RAM
The XC4000 families of Field-Programmable Gate Arrays
(FPGAs) provide the benefits of custom CMOS VLSI, while
avoiding the initial cost, time delay, and inherent risk of a
conventional masked gate array.
– Dedicated high-speed carry-propagation circuit
– Wide edge decoders
The XC4000 families provide a regular, flexible, program-
mable architecture of Configurable Logic Blocks (CLBs),
– Hierarchy of interconnect lines
interconnected by a powerful hierarchy of versatile routing
– Internal 3-state bus capability
resources, and surrounded by a perimeter of program-
– Eight global low-skew clock or signal distribution
mable Input/Output Blocks (IOBs).
network
Flexible Array Architecture
XC4000-family devices have generous routing resources to
accommodate the most complex interconnect patterns.
– Programmable logic blocks and I/O blocks
XC4000A devices have reduced sets of routing resources,
– Programmable interconnects and wide decoders
sufficient for their smaller size. XC4000H high I/O devices
Sub-micron CMOS Process
– High-speed logic and Interconnect
maintain the same routing resources and CLB structure as
the XC4000 family, while nearly doubling the available I/O.
– Low power consumption
The devices are customized by loading configuration data
Systems-Oriented Features
– IEEE 1149.1-compatible boundary-scan logic support
– Programmable output slew rate
– Programmable input pull-up or pull-down resistors
into the internal memory cells. The FPGA can either actively
read its configuration data out of external serial or byte-
parallel PROM (master modes), or the configuration data
can be written into the FPGA (slave and peripheral modes).
– 12-mA sink current per output (XC4000 family)
The XC4000 families are supported by powerful and so-
– 24-mA sink current per output (XC4000A and
phisticated software, covering every aspect of design: from
XC4000H families)
schematic entry, to simulation, to automatic block place-
Configured by Loading Binary File
– Unlimited reprogrammability
ment and routing of interconnects, and finally the creation
of the configuration bit stream.
– Six programming modes
Since Xilinx FPGAs can be reprogrammed an unlimited
XACT Development System runs on ’386/’486-type PC,
NEC PC, Apollo, Sun-4, and Hewlett-Packard 700
series
– Interfaces to popular design environments like
Viewlogic, Mentor Graphics and OrCAD
– Fully automatic partitioning, placement and routing
number of times, they can be used in innovative designs
where hardware is changed dynamically, or where hard-
ware must be adapted to different user applications. FPGAs
are ideal for shortening the design and development cycle,
but they also offer a cost-effective solution for production
rates well beyond 1000 systems per month.
– Interactive design editor for design optimization
– 288 macros, 34 hard macros, RAM/ROM compiler
Table 1. The XC4000 Families of Field-Programmable Gate Arrays
Device
XC4002A 4003/3A 4003H 4004A 4005/5A 4005H 4006 4008 4010/10D 4013/13D 4020 4025
Appr. Gate Count
CLB Matrix
Number of CLBs
Number of Flip-Flops
Max Decode Inputs
(per side)
Max RAM Bits
Number of IOBs
2,000
8x8
64
256
24
2,048
64
3,000
10 x 10
100
360
30
3,000
10 x 10
100
200
30
4,000
12 x 12
144
480
36
5,000
14 x 14
196
616
42
5,000 6,000
14 x 14 16 x 16
196 256
392 768
42 48
8,000
18 x 18
324
936
54
10,000
20 x 20
400
1,120
60
13,000
24 x 24
576
1,536
72
20,000
28 x 28
784
2,016
84
25,000
32 x 32
1,024
2,560
96
3,200 3,200 4,608 6,272 6,272 8,192 10,368 12,800* 18,432* 25,088 32,768
80 160 96 112 192 128 144 160 192 224 256
*XC4010D and XC4013D have no RAM
2-7

XC4013
XC4000, XC4000A, XC4000H Logic Cell Array Families
XC4000 Compared to XC3000A
For those readers already familiar with the XC3000A
family of Xilinx Field Programmable Gate Arrays, here is a
concise list of the major new features in the XC4000 family.
CLB has two independent 4-input function generators.
A third function generator combines the outputs of the
two other function generators with a ninth input.
All function inputs are swappable, all have full access;
none are mutually exclusive.
CLB has very fast arithmetic carry capability.
CLB function generator look-up table can also be used as
high-speed RAM.
CLB flip-flops have asynchronous set or reset.
CLB has four outputs, two flip-flops, two combinatorial.
CLB connections symmetrically located on all four edges.
IOB has more versatile clocking polarity options.
IOB has programmable input set-up time:
long to avoid potential hold time problems,
short to improve performance.
IOB has Longline access through its own TBUF.
Outputs are n-channel only, lower VOH increases speed.
XC4000 outputs can be paired to double sink current to
24 mA. XC4000A and XC4000H outputs can each
sink 24 mA, can be paired for 48 mA sink current.
IEEE 1149.1- type boundary scan is supported in the I/O.
Wide decoders on all four edges of the LCA device.
Increased number of interconnect resources.
All CLB inputs and outputs have access to most inter-
connect lines.
Switch Matrices are simplified to increase speed.
Eight global nets can be used for clocking or distributing
logic signals.
TBUF output configuration is more versatile and 3-state
control less confined.
Program is single-function input pin,overrides everything.
INIT pin also acts as Configuration Error output.
Peripheral Synchronous Mode (8 bit) has been added.
Peripheral Asynchronous Mode has improved hand-
shake.
Start-up can be synchronized to any user clock (this is a
configuration option).
No Powerdown, but instead a Global 3-state input that
does not reset any flip-flops.
No on-chip crystal oscillator amplifier.
Configuration Bit Stream includes CRC error checking.
Configuration Clock can be increased to >8 MHz.
Configuration Clock is fully static, no constraint on the
maximum Low time.
Readback either ignores flip-flop content (avoids need for
masking) or it takes a snapshot of all flip-flops at the
start of Readback.
Readback has same polarity as Configuration and can be
aborted.
Table 2. Three Generations of Xilinx Field-Programmable Gate Array Families
Parameter
XC4025
XC3195A
Number of flip-flops
Max number of user I/O
Max number of RAM bits
Function generators per CLB
Number of logic inputs per CLB
Number of logic outputs per CLB
Number of low-skew global nets
Dedicated decoders
Fast carry logic
Internal 3-state drivers
Output slew-rate control
Power-down option
Crystal oscillator circuit
2,560
256
32,768
3
9
4
8
yes
yes
yes
yes
no
no
1,320
176
0
2
5
2
2
no
no
yes
yes
yes
yes
XC2018
174
74
0
2
4
2
2
no
no
no
no
yes
yes
2-8


Features ® XC4000, XC4000A, XC4000H Logic Cell A rray Families Product Description Fea tures Description • Third Generatio n Field-Programmable Gate Arrays – Ab undant flip-flops – Flexible function generators – On-chip ultra-fast RAM The XC4000 families of Field-Programma ble Gate Arrays (FPGAs) provide the ben efits of custom CMOS VLSI, while avoidi ng the initial cost, time delay, and in herent risk of a conventional masked ga te array. – Dedicated high-speed car ry-propagation circuit – Wide edge de coders The XC4000 families provide a r egular, flexible, programmable architec ture of Configurable Logic Blocks (CLBs ), – Hierarchy of interconnect lines interconnected by a powerful hierarch y of versatile routing – Internal 3- state bus capability resources, and su rrounded by a perimeter of program- Eight global low-skew clock or signal distribution mable Input/Output Block s (IOBs). network • Flexible Array A rchitecture XC4000-family devices have generous routing resources to accommodate th.
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