TP3054 COMBO Datasheet

TP3054 Datasheet PDF, Equivalent


Part Number

TP3054

Description

CODEC/Filter COMBO

Manufacture

National Semiconductor

Total Page 16 Pages
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Download TP3054 Datasheet PDF


TP3054
August 1994
TP3054 TP3057
‘‘Enhanced’’ Serial Interface
CODEC Filter COMBO Family
General Description
The TP3054 TP3057 family consists of m-law and A-law
monolithic PCM CODEC filters utilizing the A D and D A
conversion architecture shown in Figure 1 and a serial PCM
interface The devices are fabricated using National’s ad-
vanced double-poly CMOS process (microCMOS)
The encode portion of each device consists of an input gain
adjust amplifier an active RC pre-filter which eliminates very
high frequency noise prior to entering a switched-capacitor
band-pass filter that rejects signals below 200 Hz and above
3400 Hz Also included are auto-zero circuitry and a com-
panding coder which samples the filtered signal and en-
codes it in the companded m-law or A-law PCM format The
decode portion of each device consists of an expanding
decoder which reconstructs the analog signal from the
companded m-law or A-law code a low-pass filter which
corrects for the sin x x response of the decoder output and
rejects signals above 3400 Hz followed by a single-ended
power amplifier capable of driving low impedance loads
The devices require two 1 536 MHz 1 544 MHz or 2 048
MHz transmit and receive master clocks which may be
asynchronous transmit and receive bit clocks which may
vary from 64 kHz to 2 048 MHz and transmit and receive
frame sync pulses The timing of the frame sync pulses and
PCM data is compatible with both industry standard formats
Features
Y Complete CODEC and filtering system (COMBO)
including
Transmit high-pass and low-pass filtering
Receive low-pass filter with sin x x correction
Active RC noise filters
m-law or A-law compatible COder and DECoder
Internal precision voltage reference
Serial I O interface
Internal auto-zero circuitry
Y m-law 16-pin TP3054
Y A-law 16-pin TP3057
Y Designed for D3 D4 and CCITT applications
Y g5V operation
Y Low operating power typically 50 mW
Y Power-down standby mode typically 3 mW
Y Automatic power-down
Y TTL or CMOS compatible digital interfaces
Y Maximizes line interface card circuit density
Y Dual-In-Line or surface mount packages
Y See also AN-370 ‘‘Techniques for Designing with
CODEC Filter COMBO Circuits’’
Connection Diagrams
Dual-In-Line Package
Plastic Chip Carriers
Top View
TL H 5510 – 1
Order Number TP3054J or TP3057J
See NS Package Number J16A
Order Number TP3054N or TP3057N
See NS Package Number N16A
Order Number TP3054WM or TP3057WM
See NS Package Number M16B
COMBO and TRI-STATE are registered trademarks of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL H 5510
Top View
TL H 5510 – 10
Order Number TP3057V
See NS Package Number V20A
RRD-B30M125 Printed in U S A

TP3054
Block Diagram
FIGURE 1
TL H 5510 – 2
Pin Description
Symbol
Function
Symbol
Function
VBB
GNDA
Negative power supply pin
VBB e b5V g5%
Analog ground All signals are referenced
to this pin
VFRO
Analog output of the receive power ampli-
fier
VCC Positive power supply pin
VCC e a5V g5%
FSR Receive frame sync pulse which enables
BCLKR to shift PCM data into DR FSR is
an 8 kHz pulse train See Figures 2 and 3
for timing details
DR Receive data input PCM data is shifted
into DR following the FSR leading edge
BCLKR CLKSEL The bit clock which shifts data into DR af-
ter the FSR leading edge May vary from
64 kHz to 2 048 MHz Alternatively may
be a logic input which selects either
1 536 MHz 1 544 MHz or 2 048 MHz for
master clock in synchronous mode and
BCLKX is used for both transmit and re-
ceive directions (see Table I)
MCLKR PDN
Receive master clock Must be
1 536 MHz 1 544 MHz or 2 048 MHz
May be asynchronous with MCLKX but
MCLKX
FSX
BCLKX
DX
TSX
GSX
VFXIb
VFXIa
should be synchronous with MCLKX for best per-
formance When MCLKR is connected continu-
ously low MCLKX is selected for all internal tim-
ing When MCLKR is connected continuously
high the device is powered down
Transmit master clock Must be 1 536 MHz
1 544 MHz or 2 048 MHz May be asynchronous
with MCLKR Best performance is realized from
synchronous operation
Transmit frame sync pulse input which enables
BCLKX to shift out the PCM data on DX FSX is
an 8 kHz pulse train see Figures 2 and 3 for
timing details
The bit clock which shifts out the PCM data on
DX May vary from 64 kHz to 2 048 MHz but
must be synchronous with MCLKX
The TRI-STATE PCM data output which is en-
abled by FSX
Open drain output which pulses low during the
encoder time slot
Analog output of the transmit input amplifier
Used to externally set gain
Inverting input of the transmit input amplifier
Non-inverting input of the transmit input amplifi-
er
2


Features TP3054 TP3057 ‘‘Enhanced’’ Seria l Interface CODEC Filter COMBO Family August 1994 TP3054 TP3057 ‘‘Enhanc ed’’ Serial Interface CODEC Filter COMBO Family General Description The T P3054 TP3057 family consists of m-law a nd A-law monolithic PCM CODEC filters u tilizing the A D and D A conversion arc hitecture shown in Figure 1 and a seria l PCM interface The devices are fabrica ted using National’s advanced double- poly CMOS process (microCMOS) The encod e portion of each device consists of an input gain adjust amplifier an active RC pre-filter which eliminates very hig h frequency noise prior to entering a s witched-capacitor band-pass filter that rejects signals below 200 Hz and above 3400 Hz Also included are auto-zero ci rcuitry and a companding coder which sa mples the filtered signal and encodes i t in the companded m-law or A-law PCM f ormat The decode portion of each device consists of an expanding decoder which reconstructs the analog signal from the companded m-law or A-law code a low-pass.
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