SN74AHCT125

SN54AHCT125, SN74AHCT125 SCLS264P – DECEMBER 1995 – REVISED JUNE 2023 SNx4AHCT125 Quadruple Bus Buffer Gates With 3-State Outputs 1 Features Inputs are TTL-voltage compatible Latch-up performance exceeds 250 mA per JESD 17 2 Applications Enable or disable a digital signal Controlling an indicator LED Debounce a switch Eliminate slow or noisy input signals 3 Description The ’AHCT125 devices are quadruple bus buffer gates featuring independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is high. When OE is low, the respective gate passes the data from the A input to its Y output. For the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Device Information PART NUMBER RATING PACKAGE(1) J (CDIP, 14) SN54AHCT125 Military W (CFP, 14) FK (LCCC, 20) D (SOIC, 14) DB (SSOP, 14) DGV (TVSOP, 14) SN74AHCT125 Commercial N (PDIP, 14) NS (SOP, 14) PW (SOP, 14) RGY (VQFN, 14) BQA (WQFN, 14) (1) For all available packages, see the orderable addendum at the end of the data sheet. Pin numbers are for D, DB, DGV, J, N, NS, PW, RGY, and W packages. Logic Diagram (Positive Logic) An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important...