XC2C384

0 R XC2C384 CoolRunner-II CPLD DS095 (v3.2) March 8, 2007 00 Features Optimized for 1.8V systems - As fast as 7.1 ns pin-to-pin delays - As low as 14 μA quiescent current Industry’s best 0.18 micron CMOS CPLD - Optimized architecture for effective logic synthesis - Multi-voltage I/O operation — 1.5V to 3.3V Available in multiple package options - 144-pin TQFP with 118 user I/O - 208-pin PQFP with 173 user I/O - 256-ball FT (1.0mm) BGA with 212 user I/O - 324-ball FG (1.0mm) BGA with 240 user I/O - Pb-free available for all packages Advanced system features - Fastest in system programming · 1.8V ISP using IEEE 1532 (JTAG) interface - IEEE1149.1 JTAG Boundary Scan Test - Optional Schmitt-trigger input (per pin) - Unsurpassed low power management · DataGATE enable (DGE) signal control - Four separate I/O banks - RealDigital 100% CMOS product term generation - Flexible clocking modes · Optional DualEDGE triggered registers · Clock divider (divide by 2,4,6,8,10,12,14,16) · CoolCLOCK - Global signal options with macrocell control · Multiple global clocks with phase selection per macrocell · Multiple global output enables · Global set/reset - Advanced design security - PLA architecture · Superior pinout retention · 100% product term routability across function block - Open-drain output option for Wired-OR and LED drive - Optional bus-hold, 3-state or weak pullup on selected I/O pins - Optional configurable grounds on unused I/Os - Mixed I/O voltages compatible with 1.5V, ...