XC3S200A FPGA Datasheet

XC3S200A Datasheet PDF, Equivalent


Part Number

XC3S200A

Description

Spartan-3A FPGA

Manufacture

Xilinx

Total Page 30 Pages
Datasheet
Download XC3S200A Datasheet


XC3S200A
0
Spartan-3A FPGA Family:
Data Sheet
DS529 December 18, 2018
0 0 Product Specification
Module 1:
Introduction and Ordering Information
DS529 (v2.1) December 18, 2018
• Introduction
• Features
• Architectural and Configuration Overview
• General I/O Capabilities
• Production Status
• Supported Packages and Package Marking
• Ordering Information
Module 2:
Spartan-3A FPGA Family: Functional
Description
DS529 (v2.1) December 18, 2018
The functionality of the Spartan®-3A FPGA family is
described in the following documents.
UG331: Spartan-3 Generation FPGA User Guide
• Clocking Resources
• Digital Clock Managers (DCMs)
• Block RAM
• Configurable Logic Blocks (CLBs)
- Distributed RAM
- SRL16 Shift Registers
- Carry and Arithmetic Logic
• I/O Resources
• Embedded Multiplier Blocks
• Programmable Interconnect
• ISE® Design Tools and IP Cores
• Embedded Processing and Control Solutions
• Pin Types and Package Overview
• Package Drawings
• Powering FPGAs
• Power Management
UG332: Spartan-3 Generation Configuration User Guide
• Configuration Overview
• Configuration Pins and Behavior
• Bitstream Sizes
• Detailed Descriptions by Mode
- Master Serial Mode using Platform Flash PROM
- Master SPI Mode using Commodity Serial Flash
- Master BPI Mode using Commodity Parallel Flash
- Slave Parallel (SelectMAP) using a Processor
- Slave Serial using a Processor
- JTAG Mode
• ISE iMPACT Programming Examples
• MultiBoot Reconfiguration
• Design Authentication using Device DNA
UG334: Spartan-3A/3AN FPGA Starter Kit User Guide
Module 3:
DC and Switching Characteristics
DS529 (v2.1) December 18, 2018
• DC Electrical Characteristics
• Absolute Maximum Ratings
• Supply Voltage Specifications
• Recommended Operating Conditions
• Switching Characteristics
• I/O Timing
• Configurable Logic Block (CLB) Timing
• Multiplier Timing
• Block RAM Timing
• Digital Clock Manager (DCM) Timing
• Suspend Mode Timing
• Device DNA Timing
• Configuration and JTAG Timing
Module 4:
Pinout Descriptions
DS529 (v2.1) December 18, 2018
• Pin Descriptions
• Package Overview
• Pinout Tables
• Footprint Diagrams
For more information on the Spartan-3A FPGA family, go to
www.xilinx.com/spartan3a
Spartan-3A FPGA
XC3S50A
XC3S200A
XC3S400A
XC3S700A
XC3S1400A
Status
Production
Production
Production
Production
Production
© Copyright 2006–2018 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and
other countries. PCI is a registered trademark of the PCI-SIG. All other trademarks are the property of their respective owners.
DS529 December 18, 2018
Product Specification
www.xilinx.com
1

XC3S200A
Spartan-3A FPGA Family: Data Sheet
2
www.xilinx.com
DS529 December 18, 2018
Product Specification


Features 0 Spartan-3A FPGA Family: Data Sheet DS 529 December 18, 2018 0 0 Product Spec ification Module 1: Introduction and O rdering Information DS529 (v2.1) Decemb er 18, 2018 • Introduction • Featur es • Architectural and Configuration Overview • General I/O Capabilities Production Status • Supported Pack ages and Package Marking • Ordering I nformation Module 2: Spartan-3A FPGA Fa mily: Functional Description DS529 (v2. 1) December 18, 2018 The functionality of the Spartan®-3A FPGA family is desc ribed in the following documents. • U G331: Spartan-3 Generation FPGA User Gu ide • Clocking Resources • Digital Clock Managers (DCMs) • Block RAM • Configurable Logic Blocks (CLBs) - Dis tributed RAM - SRL16 Shift Registers - Carry and Arithmetic Logic • I/O Reso urces • Embedded Multiplier Blocks Programmable Interconnect • ISE® D esign Tools and IP Cores • Embedded P rocessing and Control Solutions • Pin Types and Package Overview • Package Drawings • Powering FPGAs • Power Management • UG332: Spartan-3.
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