AM486 Microprocessor Datasheet

AM486 Datasheet PDF, Equivalent


Part Number

AM486

Description

32-Bit Microprocessor

Manufacture

AMD

Total Page 26 Pages
PDF Download
Download AM486 Datasheet PDF


AM486
PRELIMINARY
Am486® DX4 3-Volt Processor
Advanced
Micro
High-Performance, Clock-Selectable, 3.3 V, 32-Bit Microprocessor Devices
DISTINCTIVE CHARACTERISTICS
Operating voltage range 3.3 V ± 0.3 V
120-MHz operating frequency uses a 40-MHz
external bus
100-MHz operating frequency uses a 33-MHz
external bus
Wide range of chipsets and support available
through the AMD FusionPCSM Program
High Integration On-Chip
8-Kbyte code and data cache
Floating-point unit
Paged, virtual memory management
High-Performance Design
Frequent instructions execute in one clock
105.6-Million bytes/second burst bus at 33 MHz
128-Million bytes/second burst bus at 40 MHz
0.5-micron CMOS process technology
Dynamic bus sizing for 8, 16, and 32-bit buses
Complete 32-Bit Architecture
Address and data buses
All registers
8, 16, and 32-bit data types
Multiprocessor Support
Multiprocessor instructions
Cache consistency protocols
Support for second-level cache
Standard 168-Pin PGA Package
Supports Environmental Protection Agency’s
(EPA) “Energy Star” program
Energy management capability provides excel-
lent base for energy-efficient design
Works with a variety of energy efficient, power
managed devices
GENERAL DESCRIPTION
The Am486DX4 microprocessor is a high-performance
486 desktop solution that provides optimal price/perfor-
mance for high-end 486 power-managed systems. The
Am486DX4 CPU offers superior local bus graphics per-
formance for Microsoft® Windows®.
Using AMD’s speed-multiplying technology, the
Am486DX4 CPU and cache operate two to three times
faster than the external memory bus. It is manufactured
using AMD’s new 3.3-V CMOS process technology to
consume about 2.6 watts of power at 100 MHz or 3.2
watts at 120 MHz. This 3.3-V technology provides su-
perior solutions for low-power EPA’s Energy Star
Green PCs and portables.
The Am486DX4 processor operates with a 1X clock in-
put. This 1X clock simplifies system design by reducing
the clock frequency required by external devices. The
1X clock also reduces RF emission and simplifies clock
generation. The input signal is doubled or tripled inter-
nally to achieve the maximum 2X or 3X operating fre-
quency. The phases of the core clock are controlled by
an internal Phase Lock Loop (PLL) circuit.
This document contains information on a product under development at Advanced Micro Devices. The information is
intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
Publication#19160 Rev: D Amendment/0
Issue Date: July 1995

AM486
AMD
BLOCK DIAGRAM
PRELIMINARY
Am486 CPU Pipelined 32-Bit Microarchitecture
64-Bit Interunit Transfer Bus
32-Bit Data Bus
32-Bit Data Bus
Base/
Barrel Shifter Index
Bus
Register File
32
ALU
Segmentation
Unit
Descriptor
Registers
Limit and
Attribute
PLA
32
32
Linear Address Bus
32
PCD, PWT
Paging Unit
2
Cache Unit
Translation
Lookaside
Buffer
20
Physical
Address
8-Kbyte
Cache
128
Micro-instruction
Floating-
Point
Unit
Floating-
Point
Register
File
Central and
Protection
Test Unit
Control
ROM
Displacement Bus
32
Code
Stream
Prefetcher
32-byte
Code Queue
Instruction
Decode
Decoded
Instruction
Path
24 2 x 16 bytes
Power
Planes
Core
Clock
Clock
Multiplier
VOLDET
VCC, VSS
CLKMUL
CLK
Bus Interface
32
Address
Drivers
A31A2,
BE3BE0
Write Buffers
32 4 x 80
Data Bus D31D0
Transceivers
32 ADS, W/R, D/C, M/IO,
PCD, PWT, RDY, LOCK,
Bus Control
Request
Sequencer
PLOCK, BOFF, A20M,
BREQ, HOLD, HLDA,
RESET, INTR, NMI,
FERR, IGNNE, UP
Burst Bus
Control
Bus Size
Control
Cache
Control
Parity
Generation
and Control
Boundary
Scan
Control
BRDY, BLAST
BS16, BS8
KEN, FLUSH,
AHOLD, EADS
PCHK,
DP3DP0
TDI, TDO
TMS, TCK
19160C-001
2 Am486DX4 Microprocessor


Features PRELIMINARY Am486® DX4 3-Volt Processo r Advanced Micro High-Performance, C lock-Selectable, 3.3 V, 32-Bit Micropro cessor Devices DISTINCTIVE CHARACTERIS TICS Operating voltage range 3.3 V ± 0 .3 V — 120-MHz operating frequency us es a 40-MHz external bus — 100-MHz op erating frequency uses a 33-MHz externa l bus — Wide range of chipsets and su pport available through the AMD FusionP CSM Program High Integration On-Chip 8-Kbyte code and data cache — Float ing-point unit — Paged, virtual memor y management High-Performance Design Frequent instructions execute in one clock — 105.6-Million bytes/second bu rst bus at 33 MHz — 128-Million bytes /second burst bus at 40 MHz — 0.5-mic ron CMOS process technology — Dynamic bus sizing for 8, 16, and 32-bit buses Complete 32-Bit Architecture — Addr ess and data buses — All registers 8, 16, and 32-bit data types Multipro cessor Support — Multiprocessor instr uctions — Cache consistency protocols — Support for second-level cache Standard 168-Pin PGA Pac.
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