XC3S100E FPGA Datasheet

XC3S100E Datasheet PDF, Equivalent


Part Number

XC3S100E

Description

Spartan-3E FPGA

Manufacture

Xilinx

Total Page 30 Pages
PDF Download
Download XC3S100E Datasheet PDF


XC3S100E
1
DS312 December 14, 2018
Module 1:
Introduction and Ordering Information
DS312 (v4.2) December 14, 2018
• Introduction
• Features
• Architectural Overview
• Package Marking
• Ordering Information
Module 2:
Functional Description
DS312 (v4.2) December 14, 2018
• Input/Output Blocks (IOBs)
• Overview
• SelectIO™ Signal Standards
• Configurable Logic Block (CLB)
• Block RAM
• Dedicated Multipliers
• Digital Clock Manager (DCM)
• Clock Network
• Configuration
• Powering Spartan®-3E FPGAs
• Production Stepping
Spartan-3E FPGA Family
Data Sheet
Product Specification
Module 3:
DC and Switching Characteristics
DS312 (v4.2) December 14, 2018
• DC Electrical Characteristics
• Absolute Maximum Ratings
• Supply Voltage Specifications
• Recommended Operating Conditions
• DC Characteristics
• Switching Characteristics
• I/O Timing
• SLICE Timing
• DCM Timing
• Block RAM Timing
• Multiplier Timing
• Configuration and JTAG Timing
Module 4:
Pinout Descriptions
DS312 (v4.2) December 14, 2018
• Pin Descriptions
• Package Overview
• Pinout Tables
• Footprint Diagrams
© Copyright 2005–2018 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, Artix, Kintex, Zynq, Vivado, and other designated brands included herein are trademarks of Xilinx
in the United States and other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.
DS312 December 14, 2018
Product Specification
www.xilinx.com
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XC3S100E
8
DS312 (v4.2) December 14, 2018
Spartan-3E FPGA Family:
Introduction and Ordering Information
Product Specification
Introduction
The Spartan®-3E family of Field-Programmable Gate
Arrays (FPGAs) is specifically designed to meet the needs
of high volume, cost-sensitive consumer electronic
applications. The five-member family offers densities
ranging from 100,000 to 1.6 million system gates, as shown
in Table 1.
The Spartan-3E family builds on the success of the earlier
Spartan-3 family by increasing the amount of logic per I/O,
significantly reducing the cost per logic cell. New features
improve system performance and reduce the cost of
configuration. These Spartan-3E FPGA enhancements,
combined with advanced 90 nm process technology, deliver
more functionality and bandwidth per dollar than was
previously possible, setting new standards in the
programmable logic industry.
Because of their exceptionally low cost, Spartan-3E FPGAs
are ideally suited to a wide range of consumer electronics
applications, including broadband access, home
networking, display/projection, and digital television
equipment.
The Spartan-3E family is a superior alternative to mask
programmed ASICs. FPGAs avoid the high initial cost, the
lengthy development cycles, and the inherent inflexibility of
conventional ASICs. Also, FPGA programmability permits
design upgrades in the field with no hardware replacement
necessary, an impossibility with ASICs.
Features
• Very low cost, high-performance logic solution for
high-volume, consumer-oriented applications
• Proven advanced 90-nanometer process technology
• Multi-voltage, multi-standard SelectIO™ interface pins
• Up to 376 I/O pins or 156 differential signal pairs
• LVCMOS, LVTTL, HSTL, and SSTL single-ended signal
standards
• 3.3V, 2.5V, 1.8V, 1.5V, and 1.2V signaling
• 622+ Mb/s data transfer rate per I/O
• True LVDS, RSDS, mini-LVDS, differential HSTL/SSTL
differential I/O
• Enhanced Double Data Rate (DDR) support
• DDR SDRAM support up to 333 Mb/s
• Abundant, flexible logic resources
• Densities up to 33,192 logic cells, including optional shift
register or distributed RAM support
• Efficient wide multiplexers, wide logic
• Fast look-ahead carry logic
• Enhanced 18 x 18 multipliers with optional pipeline
• IEEE 1149.1/1532 JTAG programming/debug port
• Hierarchical SelectRAM™ memory architecture
• Up to 648 Kbits of fast block RAM
• Up to 231 Kbits of efficient distributed RAM
• Up to eight Digital Clock Managers (DCMs)
• Clock skew elimination (delay locked loop)
• Frequency synthesis, multiplication, division
• High-resolution phase shifting
• Wide frequency range (5 MHz to over 300 MHz)
• Eight global clocks plus eight additional clocks per each half
of device, plus abundant low-skew routing
• Configuration interface to industry-standard PROMs
• Low-cost, space-saving SPI serial Flash PROM
• x8 or x8/x16 parallel NOR Flash PROM
• Low-cost Xilinx® Platform Flash with JTAG
• Complete Xilinx ISE® and WebPACK™ software
MicroBlaze™ and PicoBlazeembedded processor cores
• Fully compliant 32-/64-bit 33 MHz PCI support (66 MHz in
some devices)
• Low-cost QFP and BGA packaging options
• Common footprints support easy density migration
• Pb-free packaging options
XA Automotive version available
Table 1: Summary of Spartan-3E FPGA Attributes
Device
CLB Array
System Equivalent
(One CLB = Four Slices)
Gates
Logic Cells
Rows Columns
Total
CLBs
Total
Slices
XC3S100E 100K
2,160
22
16
240 960
XC3S250E 250K
5,508
34
26
612 2,448
XC3S500E 500K
10,476
46
34 1,164 4,656
XC3S1200E 1200K 19,512
60
46 2,168 8,672
XC3S1600E 1600K 33,192
76
58 3,688 14,752
Notes:
1. By convention, one Kb is equivalent to 1,024 bits.
Distributed
RAM bits(1)
Block
RAM
bits(1)
Dedicated
Multipliers
DCMs
Maximum
User I/O
Maximum
Differential
I/O Pairs
15K
38K
73K
136K
231K
72K
216K
360K
504K
648K
4
12
20
28
36
2 108
4 172
4 232
8 304
8 376
40
68
92
124
156
© Copyright 2005–2018 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, Artix, Kintex, Zynq, Vivado, and other designated brands included herein are trademarks of Xilinx
in the United States and other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.
DS312 (v4.2) December 14, 2018
Product Specification
www.xilinx.com
Send Feedback
2


Features 1 DS312 December 14, 2018 Module 1: Intr oduction and Ordering Information DS312 (v4.2) December 14, 2018 • Introduct ion • Features • Architectural Over view • Package Marking • Ordering I nformation Module 2: Functional Descrip tion DS312 (v4.2) December 14, 2018 • Input/Output Blocks (IOBs) • Overvie w • SelectIO™ Signal Standards • Configurable Logic Block (CLB) • Bloc k RAM • Dedicated Multipliers • Dig ital Clock Manager (DCM) • Clock Netw ork • Configuration • Powering Spar tan®-3E FPGAs • Production Stepping Spartan-3E FPGA Family Data Sheet Prod uct Specification Module 3: DC and Swit ching Characteristics DS312 (v4.2) Dece mber 14, 2018 • DC Electrical Charact eristics • Absolute Maximum Ratings Supply Voltage Specifications • Re commended Operating Conditions • DC C haracteristics • Switching Characteri stics • I/O Timing • SLICE Timing DCM Timing • Block RAM Timing • Multiplier Timing • Configuration and JTAG Timing Module 4: Pinout Descriptions DS312 (v4.2) December 14, 2018 • Pin Des.
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