XC3S1200E

1 DS312 December 14, 2018 Module 1: Introduction and Ordering Information DS312 (v4.2) December 14, 2018 Introduction Features Architectural Overview Package Marking Ordering Information Module 2: Functional Description DS312 (v4.2) December 14, 2018 Input/Output Blocks (IOBs) Overview SelectIO™ Signal Standards Configurable Logic Block (CLB) Block RAM Dedicated Multipliers Digital Clock Manager (DCM) Clock Network Configuration Powering Spartan®-3E FPGAs Production Stepping Spartan-3E FPGA Family Data Sheet Product Specification Module 3: DC and Switching Characteristics DS312 (v4.2) December 14, 2018 DC Electrical Characteristics Absolute Maximum Ratings Supply Voltage Specifications Recommended Operating Conditions DC Characteristics Switching Characteristics I/O Timing SLICE Timing DCM Timing Block RAM Timing Multiplier Timing Configuration and JTAG Timing Module 4: Pinout Descriptions DS312 (v4.2) December 14, 2018 Pin Descriptions Package Overview Pinout Tables Footprint Diagrams © Copyright 2005–2018 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, Artix, Kintex, Zynq, Vivado, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners. DS312 December 14, 2018 Product Specification www.xilinx.com Send Feedback 1 ...