CS48560

CS485xx CS485xx Family Data Sheet Features  Cost-effective, High-performance 32-bit DSP  300,000,000 MAC/S (multiply accumulates per second)  Dual MAC cycles per clock  72-bit accumulators are the most accurate in the industry  24k x 32 SRAM, 2k blocks - assignable to data or program  Internal ROM contains a variety of configurable sound enhancement feature sets  8-channel internal DMA  Internal watch-dog DSP lock-up prevention  DSP Tool Set w/ Private Keys for Protecting Customer IP  Configurable Serial Audio Inputs/Outputs  Configurable for all input/output types  Maximum 32-bit @ 192 kHz  Supports 32-bit audio sample I/O between DSP chips  TDM input modes (multiple channels on same line)  192 kHz SPDIF transmitter  Multi-channel DSD direct stream digital SACD input  Supports Two Different Input Fs Sample Rates  Output can be master or slave  Dual processing path capability  Input supports dual domain slave clocking  Hardware assist time sampling for sample rate conversion  Integrated Clock Manager/PLL  Can operate from external crystal, external oscillator  Input Fs Auto Detection  Host & Boot via Serial Interface  Configurable GPIOs and External Interrupt Input  1.8V Core and a 3.3V I/O that is tolerant to 5V input  Low-power Mode  “Energy Star® Ready” in low-power mode, 268 µW in standby Differentiating from the legacy Cirrus multi-standard, multi-channel decoders, this new CS485xx family is still based on the same high-performance 32-bit ...