Document
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Features
• QuadPort™ datapath switching element (DSE) family allows four independent ports of access for data path management and switching
• High-bandwidth data throughput up to 10 Gb/s • 133-MHz[1] port speed x 18-bit-wide interface × 4 ports • High-speed clock to data access 4.2 ns (max.) • Synchronous pipelined devices
— 1-Mb, ½-Mb, and ¼-Mb switch arrays — 64K/32K/16K × 18 device options • 0.25-micron CMOS for optimum speed/power • IEEE 1149.1 JTAG boundary scan • Width and depth expansion capabilities
QuadPort DSE Family Applications
CY7C0430BV CY7C04312BV CY7C04314BV
10 Gb/s 3.3V QuadPort™ DSE Family
• BIST (Built-In Self-Test) controller • Dual Chip Enables on all ports for easy depth expansion • Separate upper-byte and lower-byte controls on all
ports • Simple array partitioning (CY7C0430BV only)
— Internal mask register controls counter wrap-around — Counter-Interrupt flags to indicate wrap-around — Counter and mask registers readback on address • 272-ball BGA package (27-mm × 27-mm × 1.27-mm ball pitch) • Commercial and industrial temperature ranges • 3.3V low operating power — Active = 750 mA (maximum) — Standby = 15 mA (maximum
PORT 1
PORT 3
PORT 2
BUFFERED SWITCH
PORT 4
PORT 2
PORT 1
PORT 3
PORT 4
REDUNDANT DATA MIRROR
Note: 1. fMAX2 for commercial is 135 MHz and for industrial is 133 MHz.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-06027 Rev. *A
Revised May 14, 2002
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PORT 1
PORT 2
PORT 4
PORT 3
DATA PATH AGGREGATOR Processor 1
CY7C0430BV CY7C04312BV CY7C04314BV
Pre-processed DATA Path QuadPort DSE Family
Processed DATA Path
Processor 2
DATA PATH MANAGER FOR PARALLEL PACKET PROCESSING
PORT 1 PORT 2
Queue #1 Queue #2
PORT 3 PORT 4
DATA CLASSIFICATION ENGINE
Functional Description
The CY7C043XXBV is a family of 10 Gb/s, true four-ported Datapath Switching Elements with port speeds of up to 133 MHz[1]. The members of the family include 1-Mb (64K ×18), ½-Mb (32K x18), and ¼-Mb (16K × 18) options. All four ports may be clocked at independent frequencies from one another. Simultaneous reads are allowed for accesses to the same address location; however, simultaneous reading and writing to the same address is not allowed. Any port can write to a certain location while other ports are reading that location simultaneously, if the timing spec for port to port delay (tCCS) is met. The result of writing to the same location by more than one port at the same time is undefined.
Data is registered for decreased cycle time. Clock to data valid tCD2 = 4.2 ns. Each port contains a burst counter on the input
address register. After externally loading the counter with the initial address the counter will self-increment the address internally (more details to follow). The internal write pulse width is independent of the duration of the R/W input signal. The internal write pulse is self-timed to allow the shortest possi.