CY7C04314BV DSE Datasheet

CY7C04314BV Datasheet PDF, Equivalent


Part Number

CY7C04314BV

Description

10 Gb/s 3.3V QuadPort DSE

Manufacture

Cypress

Total Page 30 Pages
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Download CY7C04314BV Datasheet PDF


CY7C04314BV
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Features
QuadPort™ datapath switching element (DSE) family
allows four independent ports of access for data path
management and switching
• High-bandwidth data throughput up to 10 Gb/s
• 133-MHz[1] port speed x 18-bit-wide interface × 4 ports
• High-speed clock to data access 4.2 ns (max.)
Synchronous pipelined devices
1-Mb, ½-Mb, and ¼-Mb switch arrays
64K/32K/16K × 18 device options
0.25-micron CMOS for optimum speed/power
IEEE 1149.1 JTAG boundary scan
Width and depth expansion capabilities
QuadPort DSE Family Applications
CY7C0430BV
CY7C04312BV
CY7C04314BV
10 Gb/s 3.3V QuadPort™
DSE Family
BIST (Built-In Self-Test) controller
Dual Chip Enables on all ports for easy depth expansion
Separate upper-byte and lower-byte controls on all
ports
Simple array partitioning (CY7C0430BV only)
Internal mask register controls counter wrap-around
Counter-Interrupt flags to indicate wrap-around
Counter and mask registers readback on address
272-ball BGA package (27-mm × 27-mm × 1.27-mm ball
pitch)
Commercial and industrial temperature ranges
3.3V low operating power
Active = 750 mA (maximum)
Standby = 15 mA (maximum
PORT 1
PORT 3
PORT 2
BUFFERED SWITCH
PORT 4
PORT 2
PORT 1
PORT 3
PORT 4
REDUNDANT DATA MIRROR
Note:
1. fMAX2 for commercial is 135 MHz and for industrial is 133 MHz.
Cypress Semiconductor Corporation 3901 North First Street San Jose CA 95134 408-943-2600
Document #: 38-06027 Rev. *A
Revised May 14, 2002

CY7C04314BV
www.DataSheet4U.com
PORT 1
PORT 2
PORT 4
PORT 3
DATA PATH AGGREGATOR
Processor 1
CY7C0430BV
CY7C04312BV
CY7C04314BV
Pre-processed DATA Path QuadPort
DSE Family
Processed DATA Path
Processor 2
DATA PATH MANAGER FOR
PARALLEL PACKET PROCESSING
PORT 1
PORT 2
Queue #1
Queue #2
PORT 3
PORT 4
DATA CLASSIFICATION ENGINE
Functional Description
The CY7C043XXBV is a family of 10 Gb/s, true four-ported
Datapath Switching Elements with port speeds of up to
133 MHz[1]. The members of the family include 1-Mb
(64K ×18), ½-Mb (32K x18), and ¼-Mb (16K × 18) options. All
four ports may be clocked at independent frequencies from
one another. Simultaneous reads are allowed for accesses to
the same address location; however, simultaneous reading
and writing to the same address is not allowed. Any port can
write to a certain location while other ports are reading that
location simultaneously, if the timing spec for port to port delay
(tCCS) is met. The result of writing to the same location by more
than one port at the same time is undefined.
Data is registered for decreased cycle time. Clock to data valid
tCD2 = 4.2 ns. Each port contains a burst counter on the input
address register. After externally loading the counter with the
initial address the counter will self-increment the address inter-
nally (more details to follow). The internal write pulse width is
independent of the duration of the R/W input signal. The
internal write pulse is self-timed to allow the shortest possible
cycle times.
A HIGH on CE0 or LOW on CE1 for one clock cycle will power
down the internal circuitry to reduce the static power
consumption. One cycle is required with chip enables asserted
to reactivate the outputs.
The CY7C0430BV (64K × 18 device) is the only member of
the family which contains burst contains for simple array parti-
tioning. Counter enable inputs are provided to stall the
operation of the address input and utilize the internal address
generated by the internal counter for fast interleaved memory
Document #: 38-06027 Rev. *A
Page 2 of 37


Features www.DataSheet4U.com Features • QuadPor t™ datapath switching element (DSE) f amily allows four independent ports of access for data path management and swi tching • High-bandwidth data throughp ut up to 10 Gb/s • 133-MHz[1] port sp eed x 18-bit-wide interface × 4 ports • High-speed clock to data access 4.2 ns (max.) • Synchronous pipelined de vices — 1-Mb, ½-Mb, and ¼-Mb switch arrays — 64K/32K/16K × 18 device op tions • 0.25-micron CMOS for optimum speed/power • IEEE 1149.1 JTAG bounda ry scan • Width and depth expansion c apabilities QuadPort DSE Family Applica tions CY7C0430BV CY7C04312BV CY7C04314 BV 10 Gb/s 3.3V QuadPort™ DSE Family • BIST (Built-In Self-Test) controlle r • Dual Chip Enables on all ports fo r easy depth expansion • Separate upp er-byte and lower-byte controls on all ports • Simple array partitioning (CY 7C0430BV only) — Internal mask regist er controls counter wrap-around — Cou nter-Interrupt flags to indicate wrap-around — Counter and mask registers readback on address • 272-bal.
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