AM486DX5 Microprocessor Datasheet

AM486DX5 Datasheet PDF, Equivalent


Part Number

AM486DX5

Description

Microprocessor

Manufacture

AMD

Total Page 30 Pages
Datasheet
Download AM486DX5 Datasheet


AM486DX5
PRELIMINARY
Enhanced Am486®DX
Microprocessor Family
DISTINCTIVE CHARACTERISTICS
s High-Performance Design
- Industry-standard write-back cache support
- Frequent instructions execute in one clock
- 105.6-million bytes/second burst bus at 33 MHz
- Flexible write-through and write-back address
control
- Advanced 0.35-µ CMOS-process technology
- Dynamic bus sizing for 8-, 16-, and 32-bit buses
- Supports “soft reset” capability
s High On-Chip Integration
- 16-Kbyte unified code and data cache
- Floating-point unit
- Paged, virtual memory management
s Enhanced System and Power Management
- Stop clock control for reduced power
consumption
- Industry-standard two-pin System Management
Interrupt (SMI) for power management indepen-
dent of processor operating mode and operating
system
- Static design with Auto Halt power-down support
- Wide range of chipsets supporting SMM avail-
able to allow product differentiation
s Complete 32-Bit Architecture
- Address and data buses
- All registers
- 8-, 16-, and 32-bit data types
s Standard Features
- 3-V core with 5-V tolerant I/O
- Wide range of chipsets and support available
through the AMD FusionE86SM Program
s 168-Pin PGA Package or 208-Pin SQFP Package
s IEEE 1149.1 JTAG Boundary-Scan Compatibility
GENERAL DESCRIPTION
The Enhanced Am486®DX Microprocessor Family is an hanced Am486DX microprocessor family. This results in
addition to the AMD E86 family of embedded micropro- decreased development costs and improved time to mar-
cessors. This new family enhances system performance ket.
by incorporating a 16-Kbyte write-back cache to the ex-
isting flexible clock control and enhanced SMM features
of a 486 CPU.
Table 1 shows available processors in the Enhanced
Am486DX microprocessor family. See page 54 for in-
formation on how these parts differ from other Am486
The Enhanced Am486DX microprocessor family en- processors.
ables write-back configuration through software and
cacheable access control. On-chip cache lines are con-
figurable as either write-through or write-back. The CPU
clock control feature permits the CPU clock to be stopped
Table 1. Clocking Options
under controlled conditions, allowing reduced power
consumption during system inactivity. The SMM function
Operating
Frequency
Input Clock
Available Package
is implemented with an industry standard two-pin inter-
mface.
.coSince the Enhanced Am486DX microprocessor family is
supported as an embedded product, customers can rely
t4uon continued cost reduction, a long-term supply, and
extended temperature products.
eeIn addition, customers have access to a large selection
hof inexpensive development tools, compilers, and
schipsets. A large number of PC operating systems and
taReal Time Operating Systems (RTOS) support the En-
Am486DX5-133
Am486DX5-133
Am486DX4-100
Am486DX4-100
Am486DX2-66
Am486DX2-66
.daThis document contains information on a product under development at Advanced Micro Devices. The information is
intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
wwwproduct without notice.
33 MHz
33 MHz
33 MHz
33 MHz
33 MHz
33 MHz
168-pin PGA
208-pin SQFP
168-pin PGA
208-pin SQFP
168-pin PGA
208-pin SQFP
Publication # 20736 Rev: B Amendment/0
Issue Date: March 1997

AM486DX5
BLOCK DIAGRAM
PRELIMINARY
32-Bit Data Bus
32-Bit Data Bus
32-Bit Linear Address
Barrel Shifter
Segmentation
Unit
Register File
ALU
24
Physical
Address
Descriptor
Registers
Limit and
Attribute
PLA
PCD, PWT
Paging Unit
2
Translation
Lookaside
Buffer
24
Physical
Address
Cache Unit
16-Kbyte
Cache
128
Micro-instruction
Floating
Point
Unit
Floating
Point
Register
File
Central and
Protection
Test Unit
Control
ROM
Displacement Bus
32
Code
Stream
Instruction
Decode
Decoded
Instruction
Path
24
Prefetcher
32-Byte
Code Queue
2x16 Bytes
Power
Plane
VOLDET
VCC, Vss
Clock
Interface
Clock
Generator
CLK
CLKMUL
STPCLK
Bus Interface
32
Address
Drivers
Write
Buffers
4x32
Copyback
Buffers
4x32
Writeback
Buffers
4x32
Data Bus
32 Transceivers
A31–A2
BE3–BE0
D31–D0
Bus Control
Request
Sequencer
ADS, W/R, D/C,
M/IO, PCD, PWT,
RDY, LOCK,
PLOCK, BOFF,
A20M, BREQ,
HOLD, HLDA,
RESET, INTR,
NMI, FERR, UP,
IGNNE, SMI,
SMIACT, SRESET
Burst Bus
Control
Bus Size
Control
BRDY, BLAST
BS16, BS8
Cache
Control
KEN, FLUSH,
AHOLD, CACHE,
EADS, INV,
WB/WT, HITM
Parity
Generation
and Control
JTAG
PCHK,
DP3–DP0
TDI, TCK,
TDO, TMS
2 Enhanced Am486DX Microprocessor Family


Features PRELIMINARY Enhanced Am486®DX Microproc essor Family www.DataSheet4U.com DIST INCTIVE CHARACTERISTICS s High-Performa nce Design - Industry-standard write-ba ck cache support - Frequent instruction s execute in one clock - 105.6-million bytes/second burst bus at 33 MHz - Flex ible write-through and write-back addre ss control - Advanced 0.35-µ CMOS-proc ess technology - Dynamic bus sizing for 8-, 16-, and 32-bit buses - Supports soft reset” capability s High On-Ch ip Integration - 16-Kbyte unified code and data cache - Floating-point unit - Paged, virtual memory management s Enha nced System and Power Management - Stop clock control for reduced power consum ption - Industry-standard two-pin Syst em Management Interrupt (SMI) for power management independent of processor op erating mode and operating system - Sta tic design with Auto Halt power-down su pport - Wide range of chipsets supporti ng SMM available to allow product diffe rentiation s Complete 32-Bit Architecture - Address and data buses - .
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