DF2S5.1ASL Diode Datasheet

DF2S5.1ASL Datasheet PDF, Equivalent


Part Number

DF2S5.1ASL

Description

ESD Protection Diode

Manufacture

Toshiba

Total Page 8 Pages
PDF Download
Download DF2S5.1ASL Datasheet PDF


DF2S5.1ASL
ESD Protection Diodes Silicon Epitaxial Planar
DF2S5.1ASL
DF2S5.1ASL
1. Applications
• ESD Protection
Note: This product is designed for protection against electrostatic discharge (ESD) and is not intended for any other
purpose, including, but not limited to, voltage regulation.
2. Packaging and Internal Circuit
1: Cathode
2: Anode
SL2
3. Absolute Maximum Ratings (Note) (Unless otherwise specified, Ta = 25)
Characteristics
Symbol Note
Rating
Unit
Electrostatic discharge voltage (IEC61000-4-2)(Contact)
Electrostatic discharge voltage (IEC61000-4-2)(Air)
VESD (Note 1)
±30
kV
Peak pulse power(tp = 8/20 µs)
Peak pulse current(tp = 8/20 µs)
Junction temperature
Storage temperature
PPK
IPP (Note 2)
Tj
Tstg
30
2.5
150
-55 to 150
W
A
Note: Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the
significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even
if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum
ratings.
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook
("Handling Precautions"/"Derating Concept and Methods") and individual reliability data (i.e. reliability test
report and estimated failure rate, etc).
Note 1: According to IEC61000-4-2.
Note 2: According to IEC61000-4-5.
©2015 Toshiba Corporation
1
Start of commercial production
2015-11
2015-12-11
Rev.1.0

DF2S5.1ASL
4. Electrical Characteristics (Unless otherwise specified, Ta = 25)
VRWM: Working peak reverse
voltage
VZ: Zener voltage
VBR: Reverse breakdown voltage
ZZ: Dynamic impedance
IZ: Zener current
IBR: Reverse breakdown current
IR: Reverse current
VC: Clamp voltage
IPP: Peak pulse current
RDYN: Dynamic resistance
IF: Forward current
VF: Forward voltage
DF2S5.1ASL
Fig. 4.1 Definitions of Electrical Characteristics
Characteristics
Symbol Note
Test Condition
Min Typ. Max Unit
Working peak reverse voltage
VRWM
   1.5 V
Zener voltage
(Reverse breakdown voltage)
VZ
(VBR)
IZ = 5 mA
(IBR = 5 mA)
4.8 5.1 5.4
V
Dynamic impedance
ZZ IZ = 5 mA
(IBR = 5 mA)
  70
Reverse current
IR VRWM = 1.5 V
  1 µA
Clamp voltage
VC (Note 1) IPP = 1 A
5.5
V
IPP = 2.5 A
6.5 12
Clamp voltage
VC (Note 2) ITLP = 16 A
10
V
ITLP = 30 A
13
Dynamic resistance
RDYN (Note 2)
0.2
Total capacitance
Ct (Note 3) VR = 0 V, f = 1 MHz
45 pF
Note 1: Based on IEC61000-4-5 8/20 µs pulse.
Note 2: TLP parameter: Z0 = 50 , tp = 100 ns, tr = 300 ps, averaging window: t1 = 30 ns to t2 = 60 ns,
extraction of dynamic resistance using a least-squares fit of TLP characteristics at IPP between 8 A to 16 A.
Note 3: Guaranteed by design.
©2015 Toshiba Corporation
2
2015-12-11
Rev.1.0


Features ESD Protection Diodes Silicon Epitaxial Planar DF2S5.1ASL DF2S5.1ASL 1. Appli cations • ESD Protection Note: This p roduct is designed for protection again st electrostatic discharge (ESD) and is not intended for any other purpose, in cluding, but not limited to, voltage re gulation. 2. Packaging and Internal Cir cuit 1: Cathode 2: Anode SL2 3. Abso lute Maximum Ratings (Note) (Unless oth erwise specified, Ta = 25) Characte ristics Symbol Note Rating Unit Ele ctrostatic discharge voltage (IEC61000- 4-2)(Contact) Electrostatic discharge v oltage (IEC61000-4-2)(Air) VESD (Note 1) ±30 kV Peak pulse power(tp = 8/2 0 µs) Peak pulse current(tp = 8/20 µs ) Junction temperature Storage temperat ure PPK IPP (Note 2) Tj Tstg 30 2.5 1 50 -55 to 150 W A   Note: Using continuously under heavy loads (e.g. t he application of high temperature/curr ent/voltage and the significant change in temperature, etc.) may cause this pr oduct to decrease in the reliability significantly even if the operating c.
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