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Reference Design
MSP430FR5869, MSP430FR5868, MSP430FR5867, MSP430FR58671 MSP430FR5859, MSP430FR5858, MSP430FR5857
MSP430FR5849, MSP430FR5848, MSP430FR5847, MSP430FR58471
SLASE34E – MAY 2014 – REVISED AUGUST 2018
MSP430FR586x, MSP430FR584x Mixed-Signal Microcontrollers
1 Device Overview
1.1 Features
1
• Embedded Microcontroller – 16-Bit RISC Architecture up to 16‑MHz Clock – Wide Supply Voltage Range From 3.6 V Down to 1.8 V (Minimum Supply Voltage is Restricted by SVS Levels, See the SVS Specifications)
• Optimized Ultra-Low-Power Modes – Active Mode: Approximately 100 µA/MHz – Standby (LPM3 With VLO): 0.4 µA (Typical) – Real-Time Clock (LPM3.5): 0.25 µA (Typical) (1) – Shutdown (LPM4.5): 0.02 µA (Typical)
• Ultra-Low-Power Ferroelectric RAM (FRAM) – Up to 64KB of Nonvolatile Memory – Ultra-Low-Power Writes – Fast Write at 125 ns Per Word (64KB in 4 ms) – Unified Memory = Program + Data + Storage in One Single Space – 1015 Write Cycle Endurance – Radiation Resistant and Nonmagnetic
• Intelligent Digital Peripherals – 32-Bit Hardware Multiplier (MPY) – 3-Channel Internal DMA – Real-Time Clock (RTC) With Calendar and Alarm Functions – Five 16-Bit Timers With up to Seven Capture/Compare Registers Each – 16-Bit Cyclic Redundancy Checker (CRC)
• High-Performance Analog – 16-Channel Analog Comparator – 12-Bit Analog-to-Digital Converter (ADC) With Internal Reference and Sample-and-Hold and up to 16 External Input Channels
• Multifunction Input/Output Ports – All Pins Support Capacitive Touch Capability With No Need for External Components
(1) RTC is clocked by a 3.7-pF crystal.
– Accessible Bit-, Byte-, and Word-Wise (in Pairs) – Edge-Selectable Wake From LPM on All Ports – Programmable Pullup and Pulldown on All Ports • Code Security and Encryption – Random Number Seed for Random Number
Generation Algorithms • Enhanced Serial Communication
– eUSCI_A0 and eUSCI_A1 Support – UART With Automatic Baud-Rate Detection – IrDA Encode and Decode – SPI
– eUSCI_B0 Supports – I2C With Multiple Slave Addressing – SPI
– Hardware UART and I2C Bootloader (BSL) • Flexible Clock System
– Fixed-Frequency DCO With 10 Selectable Factory-Trimmed Frequencies
– Low-Power Low-Frequency Internal Clock Source (VLO)
– 32-kHz Crystals (LFXT) – High-Frequency Crystals (HFXT) • Development Tools and Software – Free Professional Development Environments
With EnergyTrace++™ Technology – Development Kit (MSP-TS430RGZ48C) • Family Members – Device Comparison Summarizes the Available
Device Variants and Package Types • For Complete Module Descriptions, See the
MSP430FR58xx, MSP430FR59xx, and MSP430FR6xx Family User's Guide
1.2 Applications • Metering • Energy Harvested Sensor Nodes • Wearable Electronics
• Sensor Management • Data Logging
1.3 Description
The MSP430™ ultra-low-power (ULP) FRAM platform combines uniquely embedded FRAM and a holistic
ultra-low-power system architecture, allowing innovators to increase performance at lowered energy
budgets. FRAM technology combines the speed, flexibility, and endurance of SRAM with the stability and
reliability of flash at much lower power.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.
MSP430FR5869, MSP430FR5868, MSP430FR5867, MSP430FR58671 MSP430FR5859, MSP430FR5858, MSP430FR5857 MSP430FR5849, MSP430FR5848, MSP430FR5847, MSP430FR58471
SLASE34E – MAY 2014 – REVISED AUGUST 2018
www.ti.com
The MSP430 ULP FRAM portfolio consists of a diverse set of devices featuring FRAM, the ULP 16-bit MSP430 CPU, and intelligent peripherals targeted for various applications. The ULP architecture showcases seven low-power modes, optimized to achieve extended battery life in energy-challenged applications.
PART NUMBER MSP430FR5869IRGZ MSP430FR5859IRHA MSP430FR5859IDA
Device Information(1)
PACKAGE VQFN (48) VQFN (40) TSSOP (38)
BODY SIZE(2) 7 mm × 7 mm 6 mm × 6 mm 12.5 mm × 6.2 mm
(1) For the most current part, package, and ordering information for all available devices, see the Package Option Addendum in Section 9, or see the TI website at www.ti.com.
(2) The sizes shown here are approximations. For the package dimensions with tolerances, see the Mechanical Data in Section 9.
1.4 Functional Block Diagram
Figure 1-1 shows the functional block diagram of the devices.
DMA Controller 3 Channel
CPUXV2 incl. 16 Registers
EEM (S: 3 + 1) EnergyTrace++
JTAG Interface
LFXIN, LFXOUT, HFXIN HFXOUT
MCLK
Clock System
ACLK SMCLK
Comp_E
(up to 16 inputs)
ADC12_B
(up to 16 standard inputs, up to 8 differential
inputs)
Bus Control Logic
MAB MDB
P1.x, P2.x P3.x, P4.x 2x8 2x8
PJ.x 1x8
REF_A
Voltage Reference
Capacitive Touch I/O 0.