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TSPC603E Dataheets PDF



Part Number TSPC603E
Manufacturers Thomson
Logo Thomson
Description PowerPC 603e RISC Microprocessor
Datasheet TSPC603E DatasheetTSPC603E Datasheet (PDF)

TSPC603E PowerPC 603e™ RISC MICROPROCESSOR Family PID6-603e Specification DESCRIPTION The PID6-603e implementation of PC603e (after named 603e) is a low-power implementation of reduced instruction set computer (RISC) microprocessors PowerPC™ family. The 603e implements 32-bit effective addresses, integer data types of 8, 16 and 32 bits, and floating-point data types of 32 and 64 bits. The 603e is a low-power 3.3-volt design and provides four software controllable power-saving modes. The 603e i.

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TSPC603E PowerPC 603e™ RISC MICROPROCESSOR Family PID6-603e Specification DESCRIPTION The PID6-603e implementation of PC603e (after named 603e) is a low-power implementation of reduced instruction set computer (RISC) microprocessors PowerPC™ family. The 603e implements 32-bit effective addresses, integer data types of 8, 16 and 32 bits, and floating-point data types of 32 and 64 bits. The 603e is a low-power 3.3-volt design and provides four software controllable power-saving modes. The 603e is a superscalar processor capable of issuing and retiring as many as three instructions per clock. Instructions can execute out of order for increased performance ; however, the 603e makes completion appear sequential. The 603e integrates five execution units and is able to execute five instructions in parallel. The 603e provides independent on-chip, 16-Kbyte, four-way set-associative, physically addressed caches for instructions and data and on-chip instruction and data memory management units (MMUs). The MMUs contain 64-entry, two-way setassociative, data and instruction translation lookaside buffers that provide support for demand-paged virtual memory address translation and variable-sized block translation. The 603e has a selectable 32 or 64-bit data bus and a 32-bit address bus. The 603e interface protocol allows multiple masters to complete for system resources through a central external arbiter. The 603e supports single-beat and burst data transfers for memory accesses, and supports memorymapped I/O. The 603e uses an advanced, 3.3-V CMOS process technology and maintains full interface compatibility with TTL devices. The 603e integrates in system testability and debugging features through JTAG boundary-scan capability. MAIN FEATURES H 2.4 SPECint95, 2.1 SPECfp95 @ 100 MHz (estimated) H Superscalar (3 instructions per clock peak). H Dual 16KB caches. H Selectable bus clock. H 32-bit compatibility PowerPC implementation. H On chip debug support. H PD typical = 3.2 Watts (100 MHz), full operating conditions. H Nap, doze and sleep modes for power savings. H Branch folding. H 64-bit data bus (32-bit data bus option). H 4-Gbyte direct addressing range. H Pipelined single/double precision float unit. IEEE 754 compatible FPU. H IEEE P 1149-1 test mode (JTAG/C0P). H fint max = 100/120/133 MHz. H fbus max = 66 MHz. H Compatible CMOS input TTL Output. December1998 CERQUAD 240 A suffix CERQUAD 240 Ceramic Leaded Chip Carrier G suffix CBGA 255 Ceramic Ball Grid Array SCREENING / QUALITY / PACKAGING This product is manufactured in full compliance with : H MIL-STD-883 class B or According to TCS standards H Upscreenings based upon TCS standards H Full military temperature range (Tc = -55°C, Tc = +125°C) Industrial temperature range (Tc = –40°C, Tc = +110°C) H VCC = 3.3 V ± 5 %. H 240 pin Cerquad or 255 pin CBGA packages 1/38 TSPC603E SUMMARY A. GENERAL DESCRIPTION . . . . . . . . . . . . . . 3 1. INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2. PIN ASSIGNMENTS . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1. CQFP 240 package . . . . . . . . . . . . . . . . . . . . . 4 2.2. CBGA package . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.3. Pinout listing . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3. SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . 8 B. DETAILED SPECIFICATIONS . . . . . . . . . . 11 1. SCOPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2. APPLICABLE DOCUMENTS . . . . . . . . . . . . . . . . 11 3. REQUIREMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1. General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.2. Design and construction . . . . . . . . . . . . . . . . 11 3.2.1. Terminal connections . . . . . . . . . . . . . . . 11 3.2.2. Lead material and finish . . . . . . . . . . . . 11 3.2.3. Package . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.3. Absolute maximum ratings . . . . . . . . . . . . . . 11 3.4. Recommended operating conditions . . . . . . 11 3.5. Thermal characteristics . . . . . . . . . . . . . . . . . 12 3.5.1. CQFP240 package . . . . . . . . . . . . . . . . 12 3.5.2. CBGA255 package . . . . . . . . . . . . . . . . 13 3.6. Power consideration . . . . . . . . . . . . . . . . . . . 14 3.6.1. Dynamic Power Management . . . . . . . 14 3.6.2. Programmable Power Modes . . . . . . . . 14 3.6.3. Power Management Modes . . . . . . . . . 14 3.6.4. Power Management Software Considerations . . . . . . . . . . . . . . . . . . . . 16 3.6.5. Power dissipation . . . . . . . . . . . . . . . . . . 16 3.7. Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4. ELECTRICAL CHARACTERISTICS . . . . . . . . . . 17 4.1. General requirements . . . . . . . . . . . . . . . . . . 17 4.2. Static characteristics . . . . . . . . . . . . . . . . . . . 17 4.3. Dynamic characteristics . . . . . . . . . . . . . . . . 18 4.3.1. Clock AC specifications . . . . . . . . .


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