TSPC603E Microprocessor Datasheet

TSPC603E Datasheet PDF, Equivalent


Part Number

TSPC603E

Description

PowerPC 603e RISC Microprocessor

Manufacture

Thomson

Total Page 30 Pages
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TSPC603E
TSPC603E
PowerPC 603eRISC MICROPROCESSOR Family
PID6-603e Specification
DESCRIPTION
The PID6-603e implementation of PC603e (after named 603e)
is a low-power implementation of reduced instruction set com-
puter (RISC) microprocessors PowerPCfamily. The 603e
implements 32-bit effective addresses, integer data types of 8,
16 and 32 bits, and floating-point data types of 32 and 64 bits.
The 603e is a low-power 3.3-volt design and provides four soft-
ware controllable power-saving modes.
The 603e is a superscalar processor capable of issuing and
retiring as many as three instructions per clock. Instructions
can execute out of order for increased performance ; however,
the 603e makes completion appear sequential. The 603e inte-
grates five execution units and is able to execute five instruc-
tions in parallel.
The 603e provides independent on-chip, 16-Kbyte, four-way
set-associative, physically addressed caches for instructions
and data and on-chip instruction and data memory manage-
ment units (MMUs). The MMUs contain 64-entry, two-way set-
associative, data and instruction translation lookaside buffers
that provide support for demand-paged virtual memory
address translation and variable-sized block translation.
The 603e has a selectable 32 or 64-bit data bus and a 32-bit
address bus. The 603e interface protocol allows multiple mas-
ters to complete for system resources through a central exter-
nal arbiter. The 603e supports single-beat and burst data
transfers for memory accesses, and supports memory-
mapped I/O.
The 603e uses an advanced, 3.3-V CMOS process technology
and maintains full interface compatibility with TTL devices.
The 603e integrates in system testability and debugging fea-
tures through JTAG boundary-scan capability.
MAIN FEATURES
H 2.4 SPECint95, 2.1 SPECfp95 @ 100 MHz (estimated)
H Superscalar (3 instructions per clock peak).
H Dual 16KB caches.
H Selectable bus clock.
H 32-bit compatibility PowerPC implementation.
H On chip debug support.
H PD typical = 3.2 Watts (100 MHz), full operating conditions.
H Nap, doze and sleep modes for power savings.
H Branch folding.
H 64-bit data bus (32-bit data bus option).
H 4-Gbyte direct addressing range.
H Pipelined single/double precision float unit.
IEEE 754 compatible FPU.
H IEEE P 1149-1 test mode (JTAG/C0P).
H fint max = 100/120/133 MHz.
H fbus max = 66 MHz.
H Compatible CMOS input
TTL Output.
December1998
CERQUAD 240
A suffix
CERQUAD 240
Ceramic Leaded Chip Carrier
G suffix
CBGA 255
Ceramic Ball Grid Array
SCREENING / QUALITY / PACKAGING
This product is manufactured in full compliance with :
H MIL-STD-883 class B or According to TCS standards
H Upscreenings based upon TCS standards
H Full military temperature range (Tc = -55°C, Tc = +125°C)
Industrial temperature range (Tc = 40°C, Tc = +110°C)
H VCC = 3.3 V ± 5 %.
H 240 pin Cerquad or 255 pin CBGA packages
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TSPC603E
TSPC603E
SUMMARY
A. GENERAL DESCRIPTION . . . . . . . . . . . . . . 3
1. INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2. PIN ASSIGNMENTS . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1. CQFP 240 package . . . . . . . . . . . . . . . . . . . . . 4
2.2. CBGA package . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.3. Pinout listing . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3. SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . 8
B. DETAILED SPECIFICATIONS . . . . . . . . . . 11
1. SCOPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2. APPLICABLE DOCUMENTS . . . . . . . . . . . . . . . . 11
3. REQUIREMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1. General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2. Design and construction . . . . . . . . . . . . . . . . 11
3.2.1. Terminal connections . . . . . . . . . . . . . . . 11
3.2.2. Lead material and finish . . . . . . . . . . . . 11
3.2.3. Package . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.3. Absolute maximum ratings . . . . . . . . . . . . . . 11
3.4. Recommended operating conditions . . . . . . 11
3.5. Thermal characteristics . . . . . . . . . . . . . . . . . 12
3.5.1. CQFP240 package . . . . . . . . . . . . . . . . 12
3.5.2. CBGA255 package . . . . . . . . . . . . . . . . 13
3.6. Power consideration . . . . . . . . . . . . . . . . . . . 14
3.6.1. Dynamic Power Management . . . . . . . 14
3.6.2. Programmable Power Modes . . . . . . . . 14
3.6.3. Power Management Modes . . . . . . . . . 14
3.6.4. Power Management Software
Considerations . . . . . . . . . . . . . . . . . . . . 16
3.6.5. Power dissipation . . . . . . . . . . . . . . . . . . 16
3.7. Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4. ELECTRICAL CHARACTERISTICS . . . . . . . . . . 17
4.1. General requirements . . . . . . . . . . . . . . . . . . 17
4.2. Static characteristics . . . . . . . . . . . . . . . . . . . 17
4.3. Dynamic characteristics . . . . . . . . . . . . . . . . 18
4.3.1. Clock AC specifications . . . . . . . . . . . . . 18
4.3.2. Input AC specifications . . . . . . . . . . . . . 19
4.3.3. Output AC specifications . . . . . . . . . . . . 20
4.4. JTAG AC timing specifications . . . . . . . . . . . 22
5. FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . 24
5.1. PowerPC registers and programming
model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.1.1. General-Purpose Registers (GPRs) . . 24
5.1.2. Floating-Point Registers (FPRs) . . . . . 24
5.1.3. Condition Register (CR) . . . . . . . . . . . . 24
5.1.4. Floating-Point Status and Control Register
(FPSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.1.5. Machine State Register (MSR) . . . . . . 24
5.1.6. Segment Registers (SRs) . . . . . . . . . . . 24
5.1.7. Special-Purpose Registers (SPRs) . . . 24
5.2. Instruction set and addressing modes . . . . 27
5.2.1. PowerPC instruction set and addressing
modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.2.2. PowerPC 603e microprocessor instruction
set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.3. Cache implementation . . . . . . . . . . . . . . . . . . 28
5.3.1. PowerPC cache characteristics . . . . . . 28
5.3.2. PowerPC 603e microprocessor cache
implementation . . . . . . . . . . . . . . . . . . . . 28
5.4. Exception model . . . . . . . . . . . . . . . . . . . . . . . 29
5.4.1. PowerPC exception model . . . . . . . . . . 29
5.4.2. PowerPC 603e microprocessor exception
model . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.5. Memory management . . . . . . . . . . . . . . . . . . 33
5.5.1. PowerPC memory management . . . . . 33
5.5.2. PowerPC 603e microprocessor memory
management . . . . . . . . . . . . . . . . . . . . . . 33
5.6. Instruction timing . . . . . . . . . . . . . . . . . . . . . . 33
6. PREPARATION FOR DELIVERY . . . . . . . . . . . . . 34
6.1. Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.2. Certificate of compliance . . . . . . . . . . . . . . . . 34
7. HANDLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8. PACKAGE MECHANICAL DATA . . . . . . . . . . . . 35
8.1. 240 pins - CQFP . . . . . . . . . . . . . . . . . . . . . . . 35
8.2. BGA package description . . . . . . . . . . . . . . . 36
8.2.1. Package parameters . . . . . . . . . . . . . . . 36
8.2.2. Mechanical dimensions of the BGA pac-
kage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
9. CLOCK RELATIONSHIPS CHOICE . . . . . . . . . . 37
10. ORDERING INFORMATION . . . . . . . . . . . . . . . . 38
2/38


Features TSPC603E PowerPC 603e™ RISC MICROPROC ESSOR Family PID6-603e Specification D ESCRIPTION The PID6-603e implementation of PC603e (after named 603e) is a low- power implementation of reduced instruc tion set computer (RISC) microprocessor s PowerPC™ family. The 603e implement s 32-bit effective addresses, integer d ata types of 8, 16 and 32 bits, and flo ating-point data types of 32 and 64 bit s. The 603e is a low-power 3.3-volt des ign and provides four software controll able power-saving modes. The 603e is a superscalar processor capable of issuin g and retiring as many as three instruc tions per clock. Instructions can execu te out of order for increased performan ce ; however, the 603e makes completion appear sequential. The 603e integrates five execution units and is able to ex ecute five instructions in parallel. Th e 603e provides independent on-chip, 16 -Kbyte, four-way set-associative, physi cally addressed caches for instructions and data and on-chip instruction and data memory management units .
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