PC755 Microprocessor Datasheet

PC755 Datasheet PDF, Equivalent


Part Number

PC755

Description

32-bit RISC Microprocessor

Manufacture

ATMEL

Total Page 30 Pages
Datasheet
Download PC755 Datasheet


PC755
Features
18.1SPECint95, Estimates 12.3 SPECfp95 at 400 MHz (PC755)
15.7SPECint95, 9SPECfp95 at 350 MHz (PC745)
733 MIPS at 400 MHz (PC755) at 641 MIPS at 350 MHz (PC745)
Selectable Bus Clock (12 CPU Bus Dividers up to 10x)
PD Typical 6.4W at 400 MHz, Full Operating Conditions
Nap, Doze and Sleep Modes for Power Savings
Superscalar (3 Instructions per Clock Cycle) Two Instruction + Branch
4 Beta Byte Virtual Memory, 4-GByte of Physical Memory
64-bit Data and 32-bit Address Bus Interface
32-KB Instruction and Data Cache
Six Independent Execution Units
Write-back and Write-through Operations
fINT max = 400 MHz (TBC)
fBUS max = 100 MHz
Voltage I/O 2.5V/3.3V; Voltage Int 2.0V
PowerPC
755/745
32-bit RISC
Microprocessor
Description
The PC755 and PC745 PowerPC® microprocessors are high-performance, low-
power, 32-bit implementations of the PowerPC Reduced Instruction Set Computer
(RISC) architecture, especially enhanced for embedded applications.
The PC755 and PC745 microprocessors differ only in that the PC755 features an
enhanced, dedicated L2 cache interface with on-chip L2 tags. The PC755 is a drop-in
replacement for the award winning PowerPC 750 microprocessor and is footprint and
user software code compatible with the MPC7400 microprocessor with AltiVec tech-
nology. The PC745 is a drop-in replacement for the PowerPC 740 microprocessor and
is also footprint and user software code compatible with the PowerPC 603e micropro-
cessor. PC755/745 microprocessors provide on-chip debug support and are fully
JTAG-compliant.
The PC745 microprocessor is pin compatible with the TSPC603e family.
PC755/745
GH suffix
HITCE 255
Ceramic Ball Grid Array
GH suffix
HITCE 360
Ceramic Ball Grid Array
G suffix
CBGA360
Ceramic Ball Grid Array
GS suffix
CI-CGA360
Ceramic Ball Grid Array with
Solder Column Interposer (SCI)
ZF suffix
PBGA255
Flip-Chip Plastic Ball Grid Array
ZF suffix
PBGA360
Flip-Chip Plastic Ball Grid Array
2138G–HIREL–05/06

PC755
Screening
This product is manufactured in full compliance with:
• HiTCE CBGA according to Atmel standards
• CBGA + CI-CGA + FC-PBGA up screenings based upon Atmel standards
• Full military temperature ranges (TJ = -55°C, +125°C)
Industrial temperature ranges (TJ = -40°C, +110°C)
1. General Description
1.1 Simplified Block Diagram
The PC755 is targeted for low power systems and supports power management features such
as doze, nap, sleep, and dynamic power management. The PC755 consists of a processor core
and an internal L2 Tag combined with a dedicated L2 cache interface and a 60x bus.
Figure 1-1. PC755 Block Diagram
Additional Features
* Time Base Counter/Decrementer
* Clock Multiplier
* JTAG/COP Interface
* Thermal/Power Management
* Performance Monitor
2 Instructions
Instruction Unit
Fetcher
Branch Processing
Unit
Instruction Queue
(6-Word)
BTIC
64-Entry
BHT
CTR
LR
Dispatch Unit
64-Bit
(2 Instructions)
Instruction MMU
SRs
(Shadow)
ITLB
IBAT
Array
128-Bit
(4 Instructions)
Tags
32-Kbyte
I Cache
Reservation Station Reservation Station Reservation Station
GPR File
Reservation Station
(2-Entry)
FPR File
Reservation Station
Integer Unit 1
+x:
Integer Unit 2
+
System Register
Unit
CR
Rename Buffers
(6)
32-Bit
Load/Store Unit
+
(EA Calculation)
Rename Buffers
(6)
64-Bit
64-Bit Floating-Point
Unit
+x:
Store Queue
FFPPSCCRR
32-Bit
32-Bit
Completion Unit
Reorder Buffer
(6-Entry)
Data MMU
SRs
(Original)
DTLB
DBAT
Array
PA EA
64-Bit
Tags
32-Kbyte
D Cache
60x Bus Interface Unit
Instruction Fetch Queue
L1 Castout Queue
Data Load Queue
32-Bit Address Bus
32-/64-Bit Data Bus
17-Bit L2 Address Bus
64-Bit L2 Data Bus
L2 Bus Interface
Unit
L2 Castout Queue
L2 Controller
L2CR
L2 Tags
Not in the PC745
2 PC755/745
2138G–HIREL–05/06


Features Features • 18.1SPECint95, Estimates 12 .3 SPECfp95 at 400 MHz (PC755) • 15.7 SPECint95, 9SPECfp95 at 350 MHz (PC745) • 733 MIPS at 400 MHz (PC755) at 641 MIPS at 350 MHz (PC745) • Selectable Bus Clock (12 CPU Bus Dividers up to 1 0x) • PD Typical 6.4W at 400 MHz, Ful l Operating Conditions • Nap, Doze an d Sleep Modes for Power Savings • Sup erscalar (3 Instructions per Clock Cycl e) Two Instruction + Branch • 4 Beta Byte Virtual Memory, 4-GByte of Physica l Memory • 64-bit Data and 32-bit Add ress Bus Interface • 32-KB Instructio n and Data Cache • Six Independent Ex ecution Units • Write-back and Write- through Operations • fINT max = 400 M Hz (TBC) • fBUS max = 100 MHz • Vol tage I/O 2.5V/3.3V; Voltage Int 2.0V P owerPC 755/745 32-bit RISC Microprocess or Description The PC755 and PC745 Pow erPC® microprocessors are high-perform ance, lowpower, 32-bit implementations of the PowerPC Reduced Instruction Set Computer (RISC) architecture, especially enhanced for embedded applications. The PC755 and PC7.
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