TSPC750A

34 TSPC750A/740A PowerPC750A/740A RISC MICROPROCESSOR Family Pid8t–750A/740A Specification DESCRIPTION . The TSPC750A and TSPC740A microprocessor (after named 750A/740A) are low–power implementations of the PowerPC Reduced Instruction Set Computer (RISC) architecture. The 750A/740A microprocessors designs are superscalar, capable of issuing three instructions per clock cycle into six independent execution units The 740A/750A microprocessors uses a 2,6/3,3–volts CMOS process technology and maintains full interface compatibility with TTL devices. The 750A/740A provides four software controlable power– saving modes and a thermal assist unit management. The 750A/740A microprocessors have separate 32–Kbyte, physically–addressed instruction and data caches and differ only in that the 750A features a dedicated L2 cache interface with on–chip L2 tags. Both are software and bus–compatible with the PowerPC603 and PowerPC604 families, and are fully JTAG compliant. The TSPC740A microprocessor is pin compatible with the TSPC603e family. G suffix CBGA255 and CBGA360 Ceramic Ball Grid Array MAIN FEATURES H 12.4SPECint95,8.4SPECfp95 @266Mhz (TSPC750A) w/1MB L2 @133Mhz H 11.5SPECint95,6.9SPECfp95 @266Mhz (TSPC740A) H 488 MIPS @ 266Mhz H Selectable bus clock (11 CPU bus dividers up to 8x) H PD typical 4,2W @ 200Mhz, full operating conditions. H Nap, doze and sleep modes for power savings H Superscalar (3 instructions per clock cycle) H 4G–Byte direct addressing range. H 64–bit data and 3...