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LAMXO640E Dataheets PDF



Part Number LAMXO640E
Manufacturers Lattice Semiconductor
Logo Lattice Semiconductor
Description LA-MachXO Automotive
Datasheet LAMXO640E DatasheetLAMXO640E Datasheet (PDF)

LA-MachXO Automotive Family Data Sheet DS1003 Version 01.5, November 2007 LA-MachXO Automotive Family Data Sheet Introduction April 2006 Features ■ Non-volatile, Infinitely Reconfigurable • Instant-on – powers up in microseconds • Single chip, no external configuration memory required • Excellent design security, no bit stream to intercept • Reconfigure SRAM based logic in milliseconds • SRAM and non-volatile memory programmable through JTAG port • Supports background programming of non-volatile m.

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LA-MachXO Automotive Family Data Sheet DS1003 Version 01.5, November 2007 LA-MachXO Automotive Family Data Sheet Introduction April 2006 Features ■ Non-volatile, Infinitely Reconfigurable • Instant-on – powers up in microseconds • Single chip, no external configuration memory required • Excellent design security, no bit stream to intercept • Reconfigure SRAM based logic in milliseconds • SRAM and non-volatile memory programmable through JTAG port • Supports background programming of non-volatile memory ■ AEC-Q100 Tested and Qualified ■ Sleep Mode • Allows up to 100x static current reduction ■ TransFR™ Reconfiguration (TFR) • In-field logic update while system operates ■ High I/O to Logic Density • 256 to 2280 LUT4s • 73 to 271 I/Os with extensive package options • Density migration supported • Lead free/RoHS compliant packaging ■ Embedded and Distributed Memory • Up to 27.6 Kbits sysMEM™ Embedded Block RAM • Up to 7.5 Kbits distributed RAM • Dedicated FIFO control logic ■ Flexible I/O Buffer Data Sheet DS1003 • Programmable sysIO™ buffer supports wide range of interfaces: − LVCMOS 3.3/2.5/1.8/1.5/1.2 − LVTTL − PCI − LVDS, Bus-LVDS, LVPECL, RSDS ■ sysCLOCK™ PLLs • Up to two analog PLLs per device • Clock multiply, divide, and phase shifting ■ System Level Support • IEEE Standard 1149.1 Boundary Scan • Onboard oscillator • Devices operate with 3.3V, 2.5V, 1.8V or 1.2V power supply • IEEE 1532 compliant in-system programming Introduction The LA-MachXO automotive device family is optimized to meet the requirements of applications traditionally addressed by CPLDs and low capacity FPGAs: glue logic, bus bridging, bus interfacing, power-up control, and control logic. These devices bring together the best features of CPLD and FPGA devices on a single chip in AEC-Q100 tested and qualified versions. The devices use look-up tables (LUTs) and embedded block memories traditionally associated with FPGAs for flexible and efficient logic implementation. Through nonvolatile technology, the devices provide the single-chip, Table 1-1. LA-MachXO Automotive Family Selection Guide Device LAMXO256E/C LAMXO640E/C LUTs 256 640 Dist. RAM (Kbits) 2.0 6.0 EBR SRAM (Kbits) 00 Number of EBR SRAM Blocks (9 Kbits) 0 0 VCC Voltage Number of PLLs 1.2/1.8/2.5/3.3V 1.2/1.8/2.5/3.3V 00 Max. I/O 78 159 Packages 100-pin Lead-Free TQFP (14x14 mm) 78 74 144-pin Lead-Free TQFP (20x20 mm) 113 256-ball Lead-Free ftBGA (17x17 mm) 159 324-ball Lead-Free ftBGA (19x19 mm) LAMXO1200E 1200 6.25 9.2 1 1.2 1 211 73 113 211 LAMXO2280E 2280 7.5 27.6 3 1.2 2 271 73 113 211 271 © 2006 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 1-1 DS1003 Introduction_01.0 Lattice Semiconductor Introduction LA-MachXO Automotive Family Data Sheet high-security, instant-on capabilities traditionally associated with CPLDs. Finally, advanced process technology and careful design will provide the high pin-to-pin performance also associated with CPLDs. The ispLEVER® design tools from Lattice allow complex designs to be efficiently implemented using the LAMachXO automotive family of devices. Popular logic synthesis tools provide synthesis library support for LAMachXO. The ispLEVER tools use the synthesis tool output along with the constraints from its floor planning tools to place and route the design in the LA-MachXO device. The ispLEVER tool extracts the timing from the routing and back-annotates it into the design for timing verification. 1-2 LA-MachXO Automotive Family Data Sheet Architecture February 2007 Data Sheet DS1003 Architecture Overview The LA-MachXO family architecture contains an array of logic blocks surrounded by Programmable I/O (PIO). Some devices in this family have sysCLOCK PLLs and blocks of sysMEM™ Embedded Block RAM (EBRs). Figures 2-1, 2-2, and 2-3 show the block diagrams of the various family members. The logic blocks are arranged in a two-dimensional grid with rows and columns. The EBR blocks are arranged in a column to the left of the logic array. The PIO cells are located at the periphery of the device, arranged into Banks. The PIOs utilize a flexible I/O buffer referred to as a sysIO interface that supports operation with a variety of interface standards. The blocks are connected with many vertical and horizontal routing channel resources. The place and route software tool automatically allocates these routing resources. There are two kinds of logic blocks, the Programmable Functional Unit (PFU) and the Programmable Functional unit without RAM (PFF). The PFU contains the building blocks for logic, arithmetic, RAM, ROM, and.


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