LAMXO640C Automotive Datasheet

LAMXO640C Datasheet PDF, Equivalent


Part Number

LAMXO640C

Description

LA-MachXO Automotive

Manufacture

Lattice Semiconductor

Total Page 30 Pages
Datasheet
Download LAMXO640C Datasheet


LAMXO640C
LA-MachXO Automotive Family Data Sheet
DS1003 Version 01.5, November 2007

LAMXO640C
LA-MachXO Automotive Family Data Sheet
Introduction
April 2006
Features
Non-volatile, Infinitely Reconfigurable
• Instant-on – powers up in microseconds
• Single chip, no external configuration memory
required
• Excellent design security, no bit stream to
intercept
• Reconfigure SRAM based logic in milliseconds
• SRAM and non-volatile memory programmable
through JTAG port
• Supports background programming of
non-volatile memory
AEC-Q100 Tested and Qualified
Sleep Mode
• Allows up to 100x static current reduction
TransFR™ Reconfiguration (TFR)
• In-field logic update while system operates
High I/O to Logic Density
• 256 to 2280 LUT4s
• 73 to 271 I/Os with extensive package options
• Density migration supported
• Lead free/RoHS compliant packaging
Embedded and Distributed Memory
• Up to 27.6 Kbits sysMEM™ Embedded Block
RAM
• Up to 7.5 Kbits distributed RAM
• Dedicated FIFO control logic
Flexible I/O Buffer
Data Sheet DS1003
• Programmable sysIO™ buffer supports wide
range of interfaces:
LVCMOS 3.3/2.5/1.8/1.5/1.2
LVTTL
PCI
LVDS, Bus-LVDS, LVPECL, RSDS
sysCLOCK™ PLLs
• Up to two analog PLLs per device
• Clock multiply, divide, and phase shifting
System Level Support
• IEEE Standard 1149.1 Boundary Scan
• Onboard oscillator
• Devices operate with 3.3V, 2.5V, 1.8V or 1.2V
power supply
• IEEE 1532 compliant in-system programming
Introduction
The LA-MachXO automotive device family is optimized
to meet the requirements of applications traditionally
addressed by CPLDs and low capacity FPGAs: glue
logic, bus bridging, bus interfacing, power-up control,
and control logic. These devices bring together the best
features of CPLD and FPGA devices on a single chip in
AEC-Q100 tested and qualified versions.
The devices use look-up tables (LUTs) and embedded
block memories traditionally associated with FPGAs for
flexible and efficient logic implementation. Through non-
volatile technology, the devices provide the single-chip,
Table 1-1. LA-MachXO Automotive Family Selection Guide
Device
LAMXO256E/C LAMXO640E/C
LUTs
256 640
Dist. RAM (Kbits)
2.0 6.0
EBR SRAM (Kbits)
00
Number of EBR SRAM Blocks (9 Kbits)
0
0
VCC Voltage
Number of PLLs
1.2/1.8/2.5/3.3V 1.2/1.8/2.5/3.3V
00
Max. I/O
78 159
Packages
100-pin Lead-Free TQFP (14x14 mm) 78 74
144-pin Lead-Free TQFP (20x20 mm)
113
256-ball Lead-Free ftBGA (17x17 mm)
159
324-ball Lead-Free ftBGA (19x19 mm)
LAMXO1200E
1200
6.25
9.2
1
1.2
1
211
73
113
211
LAMXO2280E
2280
7.5
27.6
3
1.2
2
271
73
113
211
271
© 2006 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
1-1 DS1003 Introduction_01.0


Features LA-MachXO Automotive Family Data Sheet D S1003 Version 01.5, November 2007 LA-M achXO Automotive Family Data Sheet Intr oduction April 2006 Features ■ Non-v olatile, Infinitely Reconfigurable Instant-on – powers up in microseco nds • Single chip, no external confi guration memory required • Excellent design security, no bit stream to inter cept • Reconfigure SRAM based logic in milliseconds • SRAM and non-volati le memory programmable through JTAG por t • Supports background programming o f non-volatile memory ■ AEC-Q100 Test ed and Qualified ■ Sleep Mode • Al lows up to 100x static current reductio n ■ TransFR™ Reconfiguration (TFR) • In-field logic update while syste m operates ■ High I/O to Logic Densit y • 256 to 2280 LUT4s • 73 to 271 I /Os with extensive package options • Density migration supported • Lead fr ee/RoHS compliant packaging ■ Embedde d and Distributed Memory • Up to 27.6 Kbits sysMEM™ Embedded Block RAM • Up to 7.5 Kbits distributed RAM • Dedicated FIFO control logic ■ Flexible I/O Buffe.
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