ISPXPGA200

February 2010 Includes High- Performance, Low-Cost “E-Series” ispXPGA® Family Data Sheet DS1026 DISSECLOENCTTINDUEEVIDCES  Non-volatile, Infinitely Reconfigurable Instant-on - Powers up in microseconds via Microprocessor configuration interface Program E2CMOS while operating from SRAM on-chip E2CMOS® based memory No external configuration memory  Eight sysCLOCK™ Phase Locked Loops (PLLs) for Clock Management Excellent design security, no bit stream to intercept True PLL technology Reconfigure SRAM based logic in milliseconds 10MHz to 320MHz operation  High Logic Density for System-level Clock multiplication and division Integration Phase adjustment 139K to 1.25M functional gates Shift clocks in 250ps steps 160 to 496 I/O 1.8V, 2.5V, and 3.3V VCC operation  sysIO™ for High System Performance High speed memory support through SSTL and Up to 414Kb sysMEM™ embedded memory HSTL  High Performance Programmable Function Advanced buses supported through PCI, GTL+, Unit (PFU) LVDS, BLVDS, and LVPECL Four LUT-4 per PFU supports wide and narrow Standard logic supported through LVTTL, functions LVCMOS 3.3, 2.5 and 1.8 Dual flip-flops per LUT-4 for extensive pipelining 5V tolerant I/O for LVCMOS 3.3 and LVTTL Dedicated logic for adders, multipliers, multiplex- interfaces ers, and counters Programmable drive strength for series termination  Flexible Memory Resources Programmable bus maintenance Mul...